• 제목/요약/키워드: thermal bonding

검색결과 565건 처리시간 0.026초

플렉시블 전자기기 응용을 위한 미세 솔더 범프 접합부에 관한 연구 (Study on Joint of Micro Solder Bump for Application of Flexible Electronics)

  • 고용호;김민수;김택수;방정환;이창우
    • Journal of Welding and Joining
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    • 제31권3호
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    • pp.4-10
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    • 2013
  • In electronic industry, the trend of future electronics will be flexible, bendable, wearable electronics. Until now, there is few study on bonding technology and reliability of bonding joint between chip with micro solder bump and flexible substrate. In this study, we investigated joint properties of Si chip with eutectic Sn-58Bi solder bump on Cu pillar bump bonded on flexible substrate finished with ENIG by flip chip process. After flip chip bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test, thermal shock test, and bending test. After thermal shock test, we observed that crack initiated between $Cu_6Sn_5IMC$ and Sn-Bi solder and then propagated within Sn-Bi solder and/or interface between IMC and solder. On the other hands, We observed that fracture propated at interface between Ni3Sn4 IMC and solder and/or in solder matrix after bending test.

Cu-SiO2 하이브리드 본딩 (Cu-SiO2 Hybrid Bonding)

  • 서한결;박해성;김사라은경
    • 마이크로전자및패키징학회지
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    • 제27권1호
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    • pp.17-24
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    • 2020
  • As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO2 hybrid bonding.

열처리 방법에 따른 이종절연층 실리콘 기판쌍의 직접접합 (Direct Bonding of Heterogeneous Insulator Silicon Pairs using Various Annealing Method)

  • 송오성;이기영
    • 한국전기전자재료학회논문지
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    • 제16권10호
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    • pp.859-864
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    • 2003
  • We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

누적압연접합 공정에 의해 제조된 초미세립 6061 Al 합금의 열적 안정성과 건식 미끄럼 마멸 거동 (Thermal Stability and Dry Sliding Wear Behavior of Ultra-Fine Grained 6061 Al Alloy Processed by the Accumulative Roll-Bonding Process)

  • 김용석
    • 소성∙가공
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    • 제14권1호
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    • pp.71-77
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    • 2005
  • Thermal stability and dry sliding wear behavior of ultra-fine grained 6061 Al alloy fabricated by an accumulative roll-bonding (ARB) process have been investigated. After 4 ARB cycles, an ultra-fine grained microstructure of the 6061 Al alloy composed of grains with average size of 500nm, and separated mostly by high-angle boundaries was obtained. Though hardness and tensile strength of the ARB processed Al alloy increased with ARB cycles up to 4 cycles, the processed alloy exhibited decreased ductility and little strain hardening. Thermal stability of the ARB-processed microstructure was studied by annealing of the severely deformed alloy at $423K{\sim}573K$. The refined microstructure of the alloy remained stable up to 473K, and the peak aging treatment of the alloy at 450K for 8 hrs increased the thermal stability of the alloy. Sliding-wear rates of the alloy increased with the number of ARB cycles in spite of the increased hardness with the cycles. Wear mechanisms of the ultra-fine grained alloy were investigated by examining worn surfaces, wear debris, and cross-sections by a scanning electron microscopy (SEM).

12kV급 다이오드의 패키징 구조에 따른 방열 특성 연구 (Heat Dissipation Analysis of 12kV Diode by the Packaging Structure)

  • 김남균;김상철;방욱;송근호;김은동
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.1092-1095
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    • 2001
  • Steady state thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin with a thickness of 25${\mu}$m. It was assumed that the generated heat which is mainly by the on-state voltage drop, 9V for 12kV diode, is dissipated by way of the conduction through diodes layers to bonding wire and of the convection at the surface of passivating resin. It was predicted by the thermal analysis that the temperature rise of a pn junction of the 12kV diode can reach at the range of 16∼34$^{\circ}C$ under the given boundary conditions. The thickness and thermal conductivity(0.3∼3W/m-K) of the passivating resin did little effect to lower thermal resistance of the diode. As the length of the bonding wire increased, which means the distance of heat conduction path became longer, the thermal resistance increased considerably. The thermal analysis results imply that the generated heat of the diode is dissipated mainly by the conduction through the route of diode-dummy wafer-bonding wire, which suggests to minimize the length of the wire for the lowest thermal resistance.

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High Power LED 열압착 공정 특성 연구 (Thermo-ompression Process for High Power LEDs)

  • 한준모;서인재;안유민;고윤성;김태헌
    • 한국생산제조학회지
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    • 제23권4호
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    • pp.355-360
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    • 2014
  • Recently, the use of LED is increasing. This paper presents the new package process of thermal compression bonding using metal layered LED chip for the high power LED device. Effective thermal dissipation, which is required in the high power LED device, is achieved by eutectic/flip chip bonding method using metal bond layer on a LED chip. In this study, the process condition for the LED eutectic die bonder system is proposed by using the analysis program, and some experimental results are compared with those obtained using a DST (Die Shear Tester) to illustrate the reliability of the proposed process condition. The cause of bonding failures in the proposed process is also investigated experimentally.

MEMS-IR SENSOR용 식각-접합-박막증착 기반공정 (Etching-Bonding-Thin film deposition Process for MEMS-IR SENSOR Application)

  • 박윤권;주병권;박흥우;박정호;염상섭;서상희;오명환;김철주
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 G
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    • pp.2501-2503
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    • 1998
  • In this paper, the silicon-nitride membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PTO layer as a IR detection layer was deposited on the membrane and its characteristics were measured. The attack of PTO layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer can be solved through the method of bonding/etching of silicon wafer. Because the PTO layer of c-axial orientation raised thermal polarization without polling, the more integration capability can be achieved. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by IR detector, and the bonding interface was observed by SEM. The polarization characteristics and the dielectric characteristics of the PTO layer were measured, too.

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THE FABRICATION OF A PROCESS HEAT EXCHANGER FOR A SO3 DECOMPOSER USING SURFACE-MODIFIED HASTELLOY X MATERIALS

  • Park, Jae-Won;Kim, Hyung-Jin;Kim, Yong-Wan
    • Nuclear Engineering and Technology
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    • 제40권3호
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    • pp.233-238
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    • 2008
  • This study investigates the surface modification of a Hastelloy X plate and diffusion bonding in the assembly of surface modified plates. These types of plates are involved in the key processes in the fabrication of a process heat exchanger (PHE) for a $SO_3$ decomposer. Strong adhesion of a SiC film deposited onto Hastelloy X can be achieved by a thin SiC film deposition and a subsequent N ion beam bombardment followed by an additional deposition of a thicker film that prevents the Hastelloy X surface from becoming exposed to a corrosive environment through the pores. This process not only produces higher corrosion resistance as proved by electrolytic etching but also exhibits higher endurance against thermal stress above 9$900^{\circ}C$. A process for a good bonding between Hastelloy X sheets, which is essential for a good heat exchanger, was developed by diffusion bonding. The diffusion bonding was done by mechanically clamping the sheets under a heat treatment at $900^{\circ}C$. When the clamping jig consisted of materials with a thermal expansion coefficient that was equal to or less than that of the Hastelloy X, sound bonding was achieved.

자동차용 파워 모듈 패키징의 은 소재를 이용한 접합 기술 (A Review of Ag Paste Bonding for Automotive Power Device Packaging)

  • 노명훈;;정재필
    • 마이크로전자및패키징학회지
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    • 제22권4호
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    • pp.15-23
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    • 2015
  • Lead-free bonding has attracted significant attention for automotive power device packaging due to the upcoming environmental regulations. Silver (Ag) is one of the prime candidates for alternative of high Pb soldering owing to its superior electrical and thermal conductivity, low temperature sinterability, and high melting temperature after bonding. In this paper, the bonding technology by Ag paste was introduced. We classified into two Ag paste bonding according to applied pressure, and each bonding described in detail including recent studies.

3D 칩 적층을 위한 하이브리드 본딩의 최근 기술 동향 (Recent Progress of Hybrid Bonding and Packaging Technology for 3D Chip Integration)

  • 정철화;정재필
    • 반도체디스플레이기술학회지
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    • 제22권4호
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    • pp.38-47
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    • 2023
  • Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

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