• Journal of Power Electronics
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• 제11권4호
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• pp.520-526
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• 2011

This paper presents a balanced soft-chopping circuit and a modified PI controller for a high speed 4/2 Switched Reluctance Motor (SRM) with a 16 pulse per revolution encoder. The proposed balanced soft-chopping circuit can supply double the switching frequency in the fixed switching frequency of power devices to reduce current ripple. The modified PI controller uses maximum voltage, back-emf voltage and PI control modes to overcome the over-shoot current due to the time delay effect of current sensing. The maximum voltage mode can supply a fast excitation current with consideration of the hardware time delay. Then the back-emf voltage mode can suppress the current over-shoot with consideration of the feedback signal delay. Finally, the PI control mode can adjust the phase current to a desired value with a fast switching frequency due to the proposed balanced soft-chopping technology.

• 한국전기전자재료학회논문지
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• 제17권2호
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• pp.144-149
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• 2004

Register Controlled DLL with fast locking and low-power consumption, is described in this paper. Delay monitor scheme is proposed to achieve the fast locking and inverter is inserted in front of delay line to reduce the power consumption, also. Proposed DLL was fabricated in a 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS technology. The proposed delay monitor scheme enables the DLL to lock to the external clock within 4 cycles. The power consumption is 36㎽ with 3V supply voltage at 34MHz clock frequency.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.91-94
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• 2000

This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.193-197
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• 2013

This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

• 한국전자파학회논문지
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• 제19권6호
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• pp.597-602
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• 2008

본 논문은 고출력 전자파에 따른 CMOS IC 소자의 피해 효과와 회복 시간을 알아보았다. 고출력 전자파 발생 장치는 마그네트론을 사용하였고, CMOS 인버터의 오동작/부동작 판별법은 유관 식별이 가능한 LED 회로로 구성하였다. 그리고 고출력 전자파에 의해 오동작된 CMOS 인버터의 전원 전류와 회복 시간을 관찰하였다. 그 결과, 전계 강도가 약 9.9 kV/m에서의 전원 전류는 정상 전류의 2.14배가 증가하였다. 이는 래치업에 의한 CMOS 인버터가 오작동된 것을 확인할 수 있었다. 또한, COMS 인버터의 파괴는 컴포넌트, 온칩와이어, 그리고 본딩 와이어에서 다른 형태로 관찰하였다 위 실험 결과로, 전자 장비의 고출력 전자파 장해에 대한 이해를 돕는데 기초 자료로 활용될 것으로 예측된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• 제어로봇시스템학회논문지
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• 제20권7호
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• pp.750-755
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• 2014

Product shortage which causes backordering and/or lost sales cost is very popular in chemical industries, especially in commodity polymer business. This study deals with backordering cost in the supply chain optimization model under the framework of process-inventory network. Classical economic order quantity model with backordering cost suggested optimal time delay and lot size of the final product delivery. Backordering can be compensated by advancing production/transportation of it or purchasing substitute product from third party as well as product delivery delay in supply chain network. Optimal solutions considering all means to recover shortage are more complicated than the classical one. We found three different solutions depending on parametric range and variable bounds. Optimal capacity of production/transportation processes associated with the product in backordering can be different from that when the product is not in backordering. The product shipping cycle time computed in this study was smaller than that optimized by the classical EOQ model.

• 대한안전경영과학회지
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• 제8권2호
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• pp.155-167
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• 2006

본 논문은 제품공급자, 중간분배자 그리고 고객으로 구성된 2 단계 공급사슬에서 공급자가 수요 증대를 목적으로 중간분배자에게 일정기간 동안 제품대금에 대한 지불연기를 허용하는 상황을 고려하여 중간분배자의 신뢰성있는 판매가격 및 재고보충정책을 결정하는 문제를 다루었다. 문제 분석을 위하여 고려하는 제품은 시간에 따라 일정률로 퇴화한다는 가정과 함께 수송량에 따라 할인되는 수송비를 고려하여 모형을 수립하였고, 중간분배자의 수익 증대를 위한 경제적 판매가격 및 재고보충정책 결정을 위한 해법을 개발하였다.

• 한국시스템다이내믹스연구
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• 제6권2호
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• pp.25-35
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• 2005

This paper describes the mechanism for new investment to appear in waves of boom and bust causing alternative periods of over and under supply of electricity in Korean market. A system dynamics model was developed to describe the dynamic behavior of new investment in Korean market. The simulation results show the boom and bust cycle in the new investments. When the market price is high, investors decide to build new power plants. However, it takes some delay time to complete new power plants. When the new power plants are being added into the grid, the supply increases and the wholesale price begins to decrease. This causes the cancellation of new power plant or delay the construction. This mechanism causes the boom and bust cycle in new investment.