Register Controlled Delay-locked Loop using Delay Monitor Scheme
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이광희
(청주대학교 전자공학과)
노주영 (청주대학교 전자공학과) 손상희 (청주대학교 전자공학과) |
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All-digital multiphase delay locked loop for internal timing generation in embedded and/or high-speed DRAMs
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Digital delay locked loop and design technique for high-speed synchronous interface
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A Portable Digital DLL Architecture for CMOS Interface Circuit
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6H-SiC MOSFET과 디지털 IC제작
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과학기술학회마을 DOI ScienceOn |
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Partial Response Detection Technique for Driver Power Reduction in High-speed Memory - to - Processor Communications
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A study on sol-like-bulk CMOS structure operationg in low voltage with stability
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플래시메로리를 위한 Scaled SONOSFET NVSM의 프로그래밍 조건과 특성에 관한 연구
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과학기술학회마을 |
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A 2.5-ns clock access, 250MHz, 256Mb SDRAM with synchronous mirror delay
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