• Journal of Semiconductor Engineering
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• 제1권3호
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• pp.81-87
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• 2020

An instrumentation amplifier (IA) and an analog-to-digital converter (ADC) are essential circuit blocks for accurate and robust sensor readout systems. This paper introduces recent advances in radiation-hardening by design (RHBD) techniques applied for the sensor readout integrated circuits (IC), e.g., the three-op-amp IA and the successive-approximation register (SAR) ADC, operating against total ionizing dose (TID) and singe event effect (SEE) in harsh radiation environments. The radiation-hardened IA utilized TID monitoring and adaptive reference control to compensate for transistor parameter variations due to radiation effects. The radiation-hardened SAR ADC adopts delay-based double-feedback flip-flops to prevent soft errors which flips the data bits. Radiation-hardened IA and ADC were verified through compact model simulation, and fabricated CMOS chips were measured in radiation facilities to confirm their radiation tolerance.

• Journal of Semiconductor Engineering
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• 제2권1호
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• pp.99-108
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• 2021

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권1호
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• pp.202-215
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• 2023

This paper proposes a non-orthogonal multiple access (NOMA) based low-complexity relaying approach for multiuser cellular two-way relay channels (CTWRCs). In the proposed scheme, the relay detects the signal using successive interference cancellation (SIC) and re-generates the transmit signal with zero-forcing (ZF) transmit precoding. The achievable data rates of the NOMA-based multiuser two-way relaying (TWR) approach is analyzed. We further study the power allocation among different data streams to maximize the weighted sum-rate (WSR). We re-form the resultant non-convex problem into a standard monotonic program. Then, we design a polyblock outer approximation algorithm to sovle the WSR problem.The proposed optimal power allocation algorithm converges fast and it is shown that the NOMA-TWR-OPA scheme outperforms a NOMA benchmark scheme and conventional TWR schemes.

• 센서학회지
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• 제33권3호
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• pp.134-138
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• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• 한국산학기술학회논문지
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• 제15권6호
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• pp.3813-3820
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• 2014

최근 전기 사용량이 증가하면서 전력수요와 공급능력의 불균형으로 인하여 전력예비율은 점차 감소되고 있으며, 전력 공급의 신뢰성도 떨어지고 있다. 이러한 배경 하에 전기저장장치(Battery Energy Storage System)는 수요관리의 유력한 수단 가운데 하나로써 중요성이 점차 부각되고 있다. 하지만, 이차전지를 이용한 전기저장장치는 아직 고가이므로 전력계통에 도입하여 운용하기 위해서는 경제성 평가가 필수적이다. 따라서, 본 논문에서는 전력회사용 BESS의 경제성평가를 위하여 BESS를 고려한 전원베스트믹스와 축사근사법을 이용하여, BESS의 도입 전 연간 운용비용과 BESS의 도입 후 연간 운용비용을 비교하여 최적의 BESS 도입용량과 도입비용을 산정하는 알고리즘을 제안하였다. 또한, 수용가용 BESS의 경제성평가에서는 피크세이빙 및 부하평준화 기능을 통하여 수용가의 기본전기요금과 사용량전기요금을 감소시켜 최대한의 메리트를 추구하는 경제성평가 알고리즘을 제시하였다. 제안한 알고리즘을 이용하여, 모델 전력계통과 수용가(교육기관)를 대상으로 BESS의 경제성을 분석하여, 본 논문에서 제시한 알고리즘의 유용성을 확인하였다.

• 전기전자학회논문지
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• 제22권4호
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• pp.1012-1018
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• 2018

본 논문에서는 IoT 센서 처리를 위한 1.8V 공급전압의 CMOS SAR(Successive Approximation Register) A/D 변환기를 설계하였다. 본 논문에서 2개의 A/D 변환기를 병렬로 사용하여 샘플링 속도를 향상시킨 12비트 SAR A/D 변환기를 제안한다. 2개의 A/D 변환기 중 1개의 A/D 변환기는 12자리 비트를 모두 결정하고, 또 다른 A/D 변환기는 다른 A/D 변환기의 상위 6비트를 그대로 사용하여 전력소모와 스위칭 에너지를 최소화하였다. 두 번째 A/D 변환기는 상위 6비트를 결정하지 않기 때문에 컨트롤 회로와 SAR 로직이 필요하지 않아 면적을 최소화하였다. 또한 스위칭 에너지는 커패시터 용량과 C-DAC 내 전압 변화가 클수록 값이 커지는데 두 번째 A/D 변환기는 상위 6비트를 결정하지 않아 스위칭 에너지를 줄일 수 있다. 또한 커패시터 내 스플릿 커패시터 용량을 유닛 커패시터 용량과 동일하게 회로를 구성하여 C-DAC 내 공정오차를 줄일 수 있다. 제안하는 SAR A/D 변환기는 180nm CMOS 공정을 이용하여 설계하였고, 1.8V의 공급전압, 10MS/s의 변환속도, 10.2비트의 ENOB(Effective Number of Bit)이 측정되었다. 핵심 블록의 면적은 $600{\times}900um^2$, 총 전력소모는 $79.58{\mu}W$, FoM(Figure of Merit)는 6.716fJ/step로 확인할 수 있다.

• 한국음향학회지
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• 제25권7호
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• pp.339-345
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• 2006

본 논문에서는 다중 산란 현상을 해석할 수 있는 2차원 양방향 포물선 방정식 알고리즘을 제안했다. 본 논문에서 제안한 방법은 단일 산란 근사의 연속적인 적용에 바탕을 두고 있다. 각각의 거리 독립 구역의 수직 경계에 연속 조건을 적용하여 단일 산란 근사와 Split-Step Pade 법으로 거리 방향으로 전진해 가며 외향파를 계산하고 내향파 성분은 저장한다. 이어서 저장된 내향파 성분을 역 거리 방향으로 역 전파 시키고 경계에서 외향파 성분을 저장한다. 이러한 과정을 전진 방향을 바꾸어 가며 해가 수렴할 때까지 반복하여 완전 해를 계산한다. 본 논문에서 제안된 방법은 기존의 방법 [J. F. Lingevitch et al., 5. Accost. Soc. Am. 112(2), 476-480 (2002)] 에 비해 수치적으로 구현하기 간단하며 전산자원 소모가 적다.

• 산업경영시스템학회지
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• 제39권2호
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• pp.1-10
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• 2016

In this paper, we present a new way to derive the mean cycle time of the G/G/m failure prone queue when the loading of the system approaches to zero. The loading is the relative ratio of the arrival rate to the service rate multiplied by the number of servers. The system with low loading means the busy fraction of the system is low. The queueing system with low loading can be found in the semiconductor manufacturing process. Cluster tools in semiconductor manufacturing need a setup whenever the types of two successive lots are different. To setup a cluster tool, all wafers of preceding lot should be removed. Then, the waiting time of the next lot is zero excluding the setup time. This kind of situation can be regarded as the system with low loading. By employing absorbing Markov chain model and renewal theory, we propose a new way to derive the exact mean cycle time. In addition, using the proposed method, we present the cycle times of other types of queueing systems. For a queueing model with phase type service time distribution, we can obtain a two dimensional Markov chain model, which leads us to calculate the exact cycle time. The results also can be applied to a queueing model with batch arrivals. Our results can be employed to test the accuracy of existing or newly developed approximation methods. Furthermore, we provide intuitive interpretations to the results regarding the expected waiting time. The intuitive interpretations can be used to understand logically the characteristics of systems with low loading.

• International Journal of CAD/CAM
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• 제4권1호
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• pp.33-45
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• 2004

In this work, a rational procedure has been formulated for the selection of points approximating slice contours cut in LOM (Laminated Object manufacturing) with first order approximation. It is suggested that the number of points representing a slice contour can be 'minimised' or 'optmised' by equating the horizontal chordal deviation (HCD) to the user-defined surface form tolerance. It has been shown that such optimization leads to substantial reduction in slice height calculations and NC codes file size for cutting out the slices. Due to optimization, the number of contour points varies from layer to layer, so that points on successive layer contours have to be matched by four sided ruled surface patches and triangular patches. The technological problems associated with the cutting out of triangular patches have been addressed. A robust algorithm has been developed for the determination of slice height for optimum and arbitrary numbers of contour points with different strategies for error calculations. It has been shown that optimisation may even lead to detection and appropriate representation of elusive surface features. An index of optimisation has been defined and calculations of the same have been tabulated.

• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.