Journal of Sensor Science and Technology (센서학회지)

The Korean Sensors Society (한국센서학회)
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Area- and Energy-Efficient Ternary D Flip-Flop Design

  • Taeseong Kim (School of Electronic and Electrical Engineering, Kyungpook National University) ;
  • Sunmean Kim (School of Electronic and Electrical Engineering, Kyungpook National University)
  • Received : 2024.05.02
  • Accepted : 2024.05.23
  • Published : 2024.05.31
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Abstract

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

Keywords

Acknowledgement

This research was supported by the Nanomaterials Development Program through the National Research Foundation of Korea (NRF) (2022M3H4A1A04096496), funded by the Ministry of Science and ICT, Korea.

References

  1. P. Harpe, Y. Shen, H. Li, K. Pelzers, H. Xin, and E. Cantatore, "Ultra Low Power Event-Driven Sensor Interfaces", Proc. of 2023 9th International Workshop on Advances in Sensors and Interfaces (IWASI), pp. 133-137, Monopoli (Bari), Italy, 2023. 
  2. Y. Chae, C. M. Lopez, K. A. A. Makinwa, M. Ortmanns, and W. Sansen, "A Glimpse of the History of Analog ICs: A Tale of Amplifiers, Data Converters, and Sensor Interfaces", IEEE Solid-State Circuits Magazine, Vol. 15, No. 3, pp. 43-52, 2023. 
  3. M. Ren, H. Xu, C. Dong, and Z. Zhang, "Toward a Gas Sensor Interface Circuit-A Review," IEEE Sens. J., Vol. 22, No. 19, pp. 18253-18265, 2022. 
  4. R. Wang, "A Review on the Key Optimization Techniques of SAR ADC Design", Proc. of 2021 International Conference on Electronic Information Engineering and Computer Science (EIECS), pp. 951-957, Changchun, China, 2021. 
  5. H. Wang, S. Wang, Y. Yuan, and G. Zhang, "Low power consumption and low area capacitor array for 16-bit 1-MS/s SAR ADC", Proc. of 2018 IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC), pp. 1003-1006, Chongqing, China, 2018. 
  6. J. Guerber, H. Venkatram, M. Gande, A. Waters, and U. -K. Moon, "A 10-b Ternary SAR ADC With Quantization Time Information Utilization", IEEE J. Solid-State Circuits, Vol. 47, No. 11, pp. 2604-2613, 2012. 
  7. Y. S. G. Reddy and Y. Y. H. Lam, "A low-power and area-efficient radix-3 SAR ADC", Proc. of 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 146-149, Singapore, 2015. 
  8. S. Kim, S.-Y. Lee, S. Park, and S. Kang, "Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic", Proc. of 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), pp. 37-42, Fredericton, Canada, 2019. 
  9. Z. T. Sandhie, F. U. Ahmed, and M. H. Chowdhury, "Design of Ternary Master-Slave D-Flip Flop using MOS-GNRFET", Proc. of 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 554-557, Springfield, USA, 2020. 
  10. M. H. Moaiyeri, M. Nasiri, and N. Khastoo, "An efficient ternary serial adder based on carbon nanotube FETs", Eng. Sci. Technol. Int. J., Vol. 19, No. 1, pp. 271-278, 2016. 
  11. N. H. E. Weste and D. M. Harris, Principles of CMOS VLSI Design-A Circuits and Systems Perspective, 4th Edition Addison, Boston, Addison-Wesley, US, pp. 17-31, 2010. 
  12. S. Kim, S.-Y. Lee, S. Park, K. R. Kim, and S. Kang, "A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits", IEEE Trans. Circuits. Syst. I Regul. Pap., Vol. 67, No. 9, pp. 3138-3151, 2020. 
  13. D. Li, P. Chuang, and M. Sachdev, "Comparative analysis and study of metastability on high-performance flip-flops", Proc. of 2010 11th International Symposium on Quality Electronic Design, pp. 853-860, San Jose, USA, 2010.