• Title/Summary/Keyword: subthreshold-slope

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Study on the Hydrogen Treatment Effect of Vacuum deposited Pentacene Thin Film Transistors

  • Lee, Joo-Won;Chang, Jae-Won;Kim, Hoon;Kim, Kwang-Ho;Kim, Jai-Kyeong;Kim, Young-Chul;Lee, Yun-Hi;Jang, Jin;Ju, Byeong-Kwon
    • 한국정보디스플레이학회:학술대회논문집
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    • 2003.07a
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    • pp.668-672
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    • 2003
  • In order to reach the high electrical quality of organic thin film transistors (OTFTs) such as high mobility and on-off current ratio, it is strongly desirable to study the enhancement of electrical properties in OTFTs. Here, we report the novel method of hydrogen $(H_{2})$ plasma treatment to improve electrical properties in inverted staggered OTFTs based on pentacene as active layer. To certify the effect of this method, we compared the electrical properties of normal device as a reference with those of device using the novel method. In result, the normal device as a reference making no use of this method exhibited a field effect mobility of 0.055 $cm^{2}/Vs$, on/off current ratio of $10^{3}$, threshold voltage of -4.5 V, and subthreshold slope of 7.6 V/dec. While the device using the novel method exhibited a field effect mobility of 0.174 $cm^{2}/Vs$, on/off current ratio of $10^{6}$. threshold voltage of -0.5 V, and subthreshold slope of 1.49 V/dec. According to these results, we have found the electrical performances in inverted staggered pentacene TFT owing to this novel method are remarkably enhanced. So, this method plays a key role in highly improving the electric performance of OTFTs. Moreover, this method is the first time yet reported for any OTFTs

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Effects of Device Layout On The Performances of N-channel MuGFET (소자 레이아웃이 n-채널 MuGFET의 특성에 미치는 영향)

  • Lee, Sung-Min;Kim, Jin-Young;Yu, Chong-Gun;Park, Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.1
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    • pp.8-14
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    • 2012
  • The device performances of n-channel MuGFET with different fin numbers and fin widths but the total effective channel width is constant have been characterized. Two kinds of Pi-gate devices with fin number=16, fin width=55nm, and fin number=14, fin width=80nm have been used in characterization. The threshold voltage, effective electron mobility, threshold voltage roll-off, inverse subthreshold slope, PBTI, hot carrier degradation, and drain breakdown voltage have been characterized. From the measured results, the short channel effects have been reduced for narrow fin width and large fin numbers. PBTI degradation was more significant in devices with large fin number and narrow fin width but hot carrier degradation was similar for both devices. The drain breakdown voltage was higher for devices with narrow fin width and large fin numbers. With considering the short channel effects and device degradation, the devices with narrow fin width and large fin numbers are desirable in the device layout of MuGFETs.

Effect of Metal-Induced Lateral Crystallization Boundary Located in the TFT Channel Region on the Leakage Current (박막트랜지스터의 채널 내에 형성된 금속 유도 측면 결정화의 경계가 누설전류에 미치는 영향)

  • Kim, Tae-Gyeong;Kim, Gi-Beom;Yun, Yeo-Geon;Kim, Chang-Hun;Lee, Byeong-Il;Ju, Seung-Gi
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.4
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    • pp.31-37
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    • 2000
  • In the case of metal-induced lateral crystallization (MILC) for low temperature poly-Si TFT, offset length between Ni-thin film and the sides of gate could be modified to control the location of MILC boundary. Electrical characteristics were compared to analyze the effect of MILC boundary that was located either in or out of the channel region of the TFT. By removing the MILC boundary from channel region, on current, subthreshold slope and leakage current properties could be improved. When MILC boundary was located in the channel region, leakage current was reduced with electrical stress biasing. The amount of reduction increased as the channel width increased, but it was independent of the channel length.

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The Poly-Si Thin Film Transistor for Large-area TFT-LCD (대면적 TFT-LCD를 위한 다결정 실리콘 박막 트랜지스터)

  • 이정석;이용재
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.12A
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    • pp.2002-2007
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    • 1999
  • In this paper, the n-channel poly-Si thin-film transistors (poly-Si TFT's) formed by solid phase crystallization (SPC) on glass were investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, mobility, leakage current, threshold voltage, and subthreshold slope. It is done to decide to be applied on TFT-LCD with large-size and high density. In n-channel poly-Si TFT with 2, 10, 25$\mu\textrm{m}$ of channel length, the field effect mobilities are 111, 126 and 125 $\textrm{cm}^2$/V-s and leakage currents are 0.6, 0.1, and 0.02 pA/$\mu\textrm{m}$, respectively. Low threshold voltage and subthreshold slope, and good ON-OFF ratio are shown, as well. Thus, the poly-Si TFT’s used by SPC are expected to be applied on TFT-LCD with large-size and high density, which can integrate display panel and peripheral circuit on a large glass substrate.

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Study on the Electrical Characterization of Inverted Staggered Pentacene Thin Film Transistor using Hydrogen Plasma Treatment (수소 플라즈마 처리를 이용한 역스테거드형 펜타센 트랜지스터의 전기적 특성 향상에 대한 연구)

  • 장재원;이주원;김재경;김영철;주병권
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.11
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    • pp.961-968
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    • 2003
  • In order to reach the high electrical quality of organic thin film transistors (OTFTs) such as high mobility and on-off current ratio, it is strongly desirable to study the enhancement of electrical properties in OTFTs. Here, we report the novel method of hydrogen plasma treatment to improve electrical properties in inverted staggered OTFTs based on pentacene as active layer. To certify the effect of this method, we compared the electrical properties of normal device as a reference with those of device using the novel method. In result, the normal device as a reference making no use of this method exhibited a field effect mobility of 0.055 $\textrm{cm}^2$/Vs, on/off current ratio of 10$^3$, threshold voltage of -4.5 V, and subthreshold slope of 7.6 V/dec. While the device using the novel method exhibited a field effect mobility of 0.174 $\textrm{cm}^2$/Vs, on/off current ratio of 10$\^$6/, threshold voltage of -0.5 V, and subthreshold slope of 1.49 V/dec. According to these results, we have found the electrical performances in inverted staggered pentacene TFT owing to this method are remarkably enhanced. So, this method plays a key role in highly improving the electric performance of OTFTs. Moreover, this method is the first time yet reported for any OTFTs.

Single Crystal Silicon Thin Film Transistor using 501 Wafer for the Switching Device of Top Emission Type AMOLEDs (SOI 웨이퍼를 이용한 Top emission 방식 AMOLEDs의 스위칭 소자용 단결정 실리콘 트랜지스터)

  • Chang, Jae-Won;Kim, Hoon;Shin, Kyeong-Sik;Kim, Jai-Kyeong;Ju, Byeong-Kwon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.4
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    • pp.292-297
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    • 2003
  • We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

Sensitive Characteristics of Hot Carriers by Bias Stress in Hydrogenated n-chnnel Poly-silicon TFT (수소 처리시킨 N-채널 다결정 실리콘 TFT에서 스트레스인가에 의한 핫캐리어의 감지 특성)

  • Lee, Jong-Kuk;Lee, Yong-Jae
    • Journal of Sensor Science and Technology
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    • v.12 no.5
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    • pp.218-224
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    • 2003
  • The devices of n-channel poly silicon thin film transistors(TFTs) hydrogenated by plasma, $H_2$ and $H_2$/plasma processes are fabricated. The carriers sensitivity characteristics are analyzed with voltage bias stress at the gate oxide. The parametric sensitivity characteristics caused by electrical stress conditions in hydrogenated devices are investigated by measuring the drain current, threshold voltage($V_{th}$), subthreshold slope(S) and maximum transconductance($G_m$) values. As a analyzed results, the degradation characteristics in hydrogenated n-channel polysilicon thin film transistors are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The generation of traps in gate oxide are mainly dued to hot electrons injection into the gate oxide from the channel region.

Comparison of Current-Voltage Characteristics by Doping Concentrations of Nanosheet FET and FinFET (Nanosheet FET와 FinFET의 도핑 농도에 따른 전류-전압 특성 비교)

  • Ahn, Eun Seo;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2022.10a
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    • pp.121-122
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    • 2022
  • In this paper, the device performance with the structure of Nanosheet FET (NSFET) and FinFET is simulated through a three-dimensional device simulator. Current-voltage characteristics of NSFET and FinFET were simulated with respect to channel doping concentrations, and the performance such as threshold voltage and subthreshold swing extracted from the current-voltage characteristics was compared. NSFET flows more drain current and has a higher threshold voltage in current-voltage characteristics depending on channel doping concentration than that of FinFET. The subthreshold voltage swing (SS) of NSFET is steeper than that of FinFET

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Study on die electric characteristics of TIPS-pentacene transistors with variation of electrode thickness (소스/드레인 전극의 두께변화에 따른 TIPS-pentacene 트랜지스터의 전기적 특성 연구)

  • Yang, Jin-Woo;Hyung, Gun-Woo;Kim, Young-Kwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.323-324
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    • 2009
  • We investigated the electrical properties of tris-isopropylsilylethynyl (TIPS)-pentacene organic thin-film transistors (OTFTs) employing Ni/Ag source/drain electrodes. The gap height between the gate insulator and S/D electrode was controlled by changing the thickness of Ag under-layer(20, 30, 40 and 50nm). After evaporating the Ni under-layer, TIPS pentacene channel material was dropping the gap between the gate insulator and SID electrodes. The electrical proprieties of OTFT such as filed-effect mobility, on/off ratio, threshold voltage and subthreshold slope were significantly influenced by the gap height.

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The study on the electrical characteristics of oxide thin film transistors with different annealing processes (열처리 공정에 따른 산화물 박막 트랜지스터의 전기적 특성에 관한 연구)

  • Park, Yu-Jin;Oh, Min-Suk;Han, Jeong-In
    • Proceedings of the KIEE Conference
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    • 2011.07a
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    • pp.25-26
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    • 2011
  • In this paper, we investigated the effect of various annealing processes on the electrical characteristics of oxide thin film transistors (TFTs). When we annealed the TFT devices before and after source/drain (S/D) process, we could observe the different electrical characteristics of oxide TFTs. When we annealed the TFTs after deposition of transparent indium zinc oxide S/D electrodes, the annealing process decreased the contact resistance but increased the resistivity of S/D electrodes. The field effect mobility, subthreshold slope and threshold voltage of the oxide TFTs annealed before and after S/D process were 5.83 and 4.47 $cm^2$/Vs, 1.20 and 0.82 V/dec, and 3.92 and 8.33 V respectively. To analyze the differences, we measured the contact resistances and the carrier concentrations using transfer length method (TLM) and Hall measurement.

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