• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.148-152
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• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 전기전자학회논문지
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• 제20권2호
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• pp.192-195
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• 2016

본 논문에서는 저항과 BJT를 사용하지 않고 sub-threshold 영역에서 동작하는 저전압, 저전력 기준전압 발생기를 설계하였다. CTAT 전압 발생기는 두 개의 NMOS 트랜지스터를 이용하여 구성하였고, 충분한 영역의 CTAT 전압을 발생시키기 위해 바디 바이어스 회로를 이용하였다. PTAT 전압 발생기는 PTAT 전압을 생성하기 위해 MOS 트랜지스터 입력 쌍의 서로 다른 사이즈 비를 이용하는 차동증폭기 형태로 구성하였다. 제안한 회로는 $0.18-{\mu}m$ 표준 CMOS 공정으로 설계되었다. 시뮬레이션 결과로 290mV의 출력 기준 전압을 가지며, -$20^{\circ}C$ 에서 $120^{\circ}C$의 온도 변화에서 92 ppm/$^{\circ}C$의 전압 변화 지수와 전원전압 0.63V에서 15.7nW의 소모 전력을 갖는 것을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권4호
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• pp.269-274
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• 2004

Current delivery system, in which the analog current produced by a unique DAC circuit is stored into a current-memory circuit and delivered in a time-divided sequence, shows variation of output current as low as 4% in a current source data-driver IC for AM-OLED driven by a current-programmed method without any fuse repairing after fabrication. This driver IC has 54 outputs and can sink constant current as low as 3 ${\mu}A$ with 6-bit analog levels. Such a low current level without variation can hardly be obtained by an ordinary MOS transistor because the current level is in the sub-threshold region and changes exponentially with threshold voltage variation. Thus we adopted a current mirror circuit composed of bipolar transistors to supply well-controlled current within a nano-ampere range.

• 한국전자통신학회논문지
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• 제11권7호
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• pp.665-670
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• 2016

본 논문에서는 IoT(Internet of Things) 시스템의 기본 구성이 되는 센서 네트워크에 사용될 수 있는 MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 Sub-threshold 동작을 이용하는 OP-AMP(Operational amplifier) 설계를 제안한다. MOSFET의 Sub-threshold 동작은 전원전압을 낮추는 효과로 회로 시스템을 초저전력으로 유도할 수 있는 특징이 있기 때문에 배터리를 사용하는 IoT의 센서 네트워크 시스템의 초저전력화에 매우 유용한 회로설계 기술이라고 할 수 있다. $0.35{\mu}m$ 공정을 이용한 시뮬레이션 결과, VDD를 0.6 V로 설계할 수 있었으며, OP-AMP 의 Open-loop Gain은 43 dB, 또한 설계한 OP-AMP의 소비전력은 $1.3{\mu}W$가 계산되었다. 또한, Active Layout 면적은 $64{\mu}m{\times}105{\mu}m$이다. 제안한 OP-AMP는 IoT의 저전력 센서 네트워크에 다양한 응용이 가능할 것으로 기대된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.331-338
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• 2014

A charge-pump circuit using a current-bypass technique, which suppresses charge sharing and reduces the sub-threshold currents, helps to decrease phase-locked loop (PLL) jitter without resorting to a feedback amplifier. The PLL shows no stability issues and no power-up problems, which may occur when a feedback amplifier is used. The PLL is implemented in 0.11-${\mu}m$ CMOS technology to achieve 0.856-ps RMS and 8.75-ps peak-to-peak jitter, which is almost independent of ambient temperature while consuming 4 mW from a 1.2-V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.647-654
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• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

• ETRI Journal
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• 제31권5호
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• pp.585-592
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• 2009

This paper presents a method for decoding high minimal distance ($d_{min}$) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher$d_{min}$ than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high $d_{min}$, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof-of-concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25-${\mu}m$ CMOS. It outperforms an equivalent LDPC-like decoder by 1 dB at BER=$10^{-5}$ and is 44 percent smaller and consumes 28 percent less energy per decoded bit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.134-138
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• 2008

We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudo-random manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.

• 전자공학회논문지C
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• 제36C권8호
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• pp.10-21
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• 1999

본 논문에서는 12비트의 해상도와 65MHz의 변환속도를 가지면서 단일 3.3V의 공급전압으로 동작하는 전류 셀 매트릭스 구조의 CMOS D/A 변환기를 제안하였다. 설계된 CMOS D/A 변환기는 우수한 단조증가성과 빠른 정착시간을 가지는 전류 셀 매트릭스 구조의 장점을 이용하면서 기존의 D/A 변환기의 전류셀 간의 문턱전압의 부정합과 접지선의 전압 강하에 의한 오차를 감소시키기 위해 트리 구조 바이어스 회로, 대칭적 접지선 연결, 캐스코드 전류 스위치를 사용하여 구현되었다. 설계된 전류 셀 매트릭스 12비트 D/A 변환기를 $0.6{\mu}m$ CMOS n-well 공정을 이용하여 제작하였다. 제작된 DAC칩을 +3.3V 단일 공급전원을 이용하여 측정한 결과, 정착시간이 20nsec로써 50MHz의 변환속도와 35.6mW의 전력소모를 나타내었다. 또한 측정된 SNR, DNL은 각각 55 dB, ${\pm}0.5LSB$,${\pm}2LSB$를 나타내었다.