JSTS:Journal of Semiconductor Technology and Science

  • 제8권2호
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  • Pages.134-138
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  • 2008
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism

  • Lee, Hyoung-Wook (School of Electrical Engineering, Seoul National University) ;
  • Lee, Hyun-Joong (School of Electrical Engineering, Seoul National University) ;
  • Woo, Jong-Kwan (School of Electrical Engineering, Seoul National University) ;
  • Shin, Woo-Yeol (School of Electrical Engineering, Seoul National University) ;
  • Kim, Su-Hwan (School of Electrical Engineering, Seoul National University)
  • 발행 : 2008.06.30
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초록

We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudo-random manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.

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참고문헌

  1. H. Mahmoodi-Meimand and K. Roy, "A leakagetolerant high fanin dynamic circuit design style," IEEE Transactions on Circuits and Systems-I, vol. 51, no. 3, pp. 495-503, Mar. 2004 https://doi.org/10.1109/TCSI.2004.823665
  2. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Springer, 2006
  3. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamda, "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE Journal of Solid-State Circuits, vol. SC-30, pp. 847-854, Aug. 1995
  4. S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamda, "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits," IEEE Journal of Solid-State Circuits, vol. SC-32, pp. 861-869, June 1997
  5. K. Kumagai, J. Iwaki, H. Suzuki, T. Yamada, and S. Kurosawa, "A novel powering-down scheme for low Vt CMOS circuits," in Proc. of the IEEE Symposium on VLSI Circuits, pp. 44-45, 1998
  6. H. Kawaguchi, K. Nose, and T. Sakura, "A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current," IEEE Journal of Solid-State Circuits, vol. SC-35, pp. 1498-1501, Oct. 2000
  7. S. Kim, S. V. Kosonocky, and D. R. Knebel, "Understanding and Minimizing Ground Bounce In Mode Transition of Power Gating Structures," in Proceedings of the 2003 International Symposium on Low Power Electronics and Design, pp. 22-25, August 2003
  8. S. Kim, S. V. Kosonocky, D. R. Knebel, K. Stawiasz, and M. C. Papaefthymiou, "A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs," IEEE Transactions on Circuits and Systems-II, vol. 54, no. 7, pp. 586-590, July 2007 https://doi.org/10.1109/TCSII.2007.894428
  9. S. Kim, C. Choi, D.-K. Jeong, S. V. Kosonocky, and S. Park, "Reducing Ground Bounce Noise and Stabilizing the Data Retention Voltage of Power Gating Structures," IEEE Transactions on Electron Devices, vol. 55, no. 1, pp.197-205, Jan. 2008 https://doi.org/10.1109/TED.2007.911067
  10. A. Abdollahi, F. Fallah, and M. Pedram, "A robust power gating structure and power mode transition strategy for MTCMOS design," IEEE Transactions on VLSI, vol. 15, pp. 80-89, Jan. 2007 https://doi.org/10.1109/TVLSI.2007.891093