• 제목/요약/키워드: sub channel

검색결과 932건 처리시간 0.031초

UHF 대역 RFID 전파경로에서의 전파간섭 모델링 및 채널 운용 방안 제안 (Modeling of Propagation Interference and Channel Application Solution Suggestion In the UHF Band RFID Propagation Path)

  • 문영주;여선미;전부원;노형환;정명섭;오하령;성영락;박준석
    • 전기학회논문지
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    • 제57권11호
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    • pp.2047-2053
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    • 2008
  • Auto-ID industries and their services have been improved since decades ago, and radio frequency identification (RFID) has been contributing in many applications. Product management can be the foremost example. In our industrial experiences, RFID in ultra high frequency (UHF) band provides much longer interrogation ranges than that of 13.56MHz; many more applications exist thereby. There should be several interesting and useful ideas on UHF RFID; however, those ideas can be limited due to the inevitable environmental circumstances that restrict the interrogation range in shorten value. This paper discusses the propagation interference among different types of readers (e.g, mobile RFID readers in stationary reader zone) in dense-reader environment. In most cases, UHF RFIDs in Korea will be dependent on the UHF mobile RFIDs. In this sense, the UHF mobile users accidently move into the stationary reader's interrogation zone. This is serious problem. In this paper, we analyze propagation loss and propose the effective channel allocation scheme that can contribute developing less-invasive UHF RFID networks. The simulation and practical measurement process using the commercial CAD tools and measurement equipments are presented.

Single-Channel Non-Causal Speech Enhancement to Suppress Reverberation and Background Noise

  • Song, Myung-Suk;Kang, Hong-Goo
    • 한국음향학회지
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    • 제31권8호
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    • pp.487-506
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    • 2012
  • This paper proposes a speech enhancement algorithm to improve the speech intelligibility by suppressing both reverberation and background noise. The algorithm adopts a non-causal single-channel minimum variance distortionless response (MVDR) filter to exploit an additional information that is included in the noisy-reverberant signals in subsequent frames. The noisy-reverberant signals are decomposed into the parts of the desired signal and the interference that is not correlated to the desired signal. Then, the filter equation is derived based on the MVDR criterion to minimize the residual interference without bringing speech distortion. The estimation of the correlation parameter, which plays an important role to determine the overall performance of the system, is mathematically derived based on the general statistical reverberation model. Furthermore, the practical implementation methods to estimate sub-parameters required to estimate the correlation parameter are developed. The efficiency of the proposed enhancement algorithm is verified by performance evaluation. From the results, the proposed algorithm achieves significant performance improvement in all studied conditions and shows the superiority especially for the severely noisy and strongly reverberant environment.

Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

  • Patil, Ganesh C.;Qureshi, S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권1호
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    • pp.66-74
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    • 2012
  • In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

Electrical Characteristics of Single-silicon TFT Structure with Symmetric Dual-gate for Kink Effect Suppression

  • Kang Ey-Goo;Lee Dae-Yeon;Lee Chang-Hun;Kim Chang-Hun;Sung Man-Young
    • Transactions on Electrical and Electronic Materials
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    • 제7권2호
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    • pp.53-57
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    • 2006
  • In this paper, a Symmetric Dual-gate Single-Si TFT, which includes three split floating n+ zones, is simulated. This structure drastically reduces the kink-effect and improves the on-current. This is due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region. This structure allows effective reduction in the kink-effect, depending on thy length of the two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA, while that of the conventional dual-gate structure is 0.5 mA, at both 12 V drain and 7 V gate voltages. This result shows an 80% enhancement in on-current. In addition, the reduction of electric field in the channel region compared to a conventional single-gate TFT and the reduction of the output conductance in the saturation region, is observed. In addition, the reduction in hole concentration, in the channel region, in order for effectively reducing the kink-effect, is also confirmed.

Combination of Array Processing and Space-Time Coding In MC-CDMA System

  • Hung Nguyen Viet;Fernando W. A. C
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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    • pp.302-309
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    • 2004
  • The transmission capacity of wireless communication systems may become dramatically high by employ multiple transmit and receive antennas with space-time coding techniques appropriate to multiple transmit antennas. For large number of transmit antennas and at high bandwidth efficiencies, the receiver may become too complex whenever correlation across transmit antennas is introduced. Reducing decoding complexity at receiver by combining array processing and space-time codes (STC) helps a communication system using STC to overcome the big obstacle that prevents it from achieving a desired high transmission rate. Multi-carrier CDMA (MC-CDMA) allows providing good performance in a channel with high inter-symbol interference. Antenna array, STC and MC-CDMA system have a similar characteristic that transmit-receive data streams are divided into sub-streams. Thus, there may be a noticeable reduction of receiver complexity when we combine them together. In this paper, the combination of array processing and STC in MC-CDMA system over slow selective-fading channel is investigated and compared with corresponding existing MC-CDMA system using STC. A refinement of this basic structure leads to a system design principle in which we have to make a trade off between transmission rate, decoding complexity, and length of spreading code to reach a given desired design goal.

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잡음이 존재하는 채널에서 이용되는 분류 벡터 양자화 코드북의 인덱스할당기법 (Optimization of CVQ codebook index for noisy channels)

  • 한종기;김진욱
    • 한국통신학회논문지
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    • 제28권3C호
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    • pp.315-326
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    • 2003
  • 본 논문은 분류 벡터 양자화(CVQ)기법을 이용한 통신 시스템에서 채널 오류를 감소시키기 위한 인덱스벡터할당 방식을 다루고 있다. 제안된 시스템은 크게 내부 인덱스 할당방식(IIA inner index assignment)과 교차인덱스 할당방식(CIA : cross index assignment)으로 구성된다. IIA는 부(Sub)코드북 내에서 유사한 코드벡터들에 Hamming거리가 가까운 인덱스들을 할당함으로써 채널에러에 의해 발생된 화질저하를 감소시킨다. CIA는 인덱스 벡터의 클래스 정보를 나타내는 클래스 비트에 발생하는 채널 오류의 영향을 최소화할 수 있는 방법으로서 IIA에 의해 할당된 인덱스 벡터들을 수정한다. 본 논문에서 실시된 컴퓨터 모의실험은 제안된 시스템이 채널 부호화기법을 사용하지 않고도 채널 잡음을 극복할 수 있음을 보여준다.

Kink-effect 개선을 위한 세 개의 분리된 N+ 구조를 지닌 대칭형 듀얼 게이트 단결정 TFT 구조에 대한 연구 (Single-silicon TFT Structure for Kink-effect Suppression with Symmetric Dual-gate by Three Split floating N+ Zones)

  • 이대연;황상준;박상원;성만영
    • 한국전기전자재료학회논문지
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    • 제18권5호
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    • pp.423-430
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    • 2005
  • In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating $n^{+}$ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating $n^{+}$ zones, the transistor channel region is split into four zones with different lengths defined by a floating $n^{+}$ region. This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA while that of the conventional dual-gate structure is 0.5 mA at a 12 V drain voltage and a 7 V gate voltage. This results show a $80 {\%}$ enhancement in on-current by adding two floating $n^{+}$ zones. Moreover we observed the reduction of electric field In the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

A dual-path high linear amplifier for carrier aggregation

  • Kang, Dong-Woo;Choi, Jang-Hong
    • ETRI Journal
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    • 제42권5호
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    • pp.773-780
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    • 2020
  • A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

High-performance thin-film transistor with a novel metal oxide channel layer

  • Son, Dae-Ho;Kim, Dae-Hwan;Kim, Jung-Hye;Sung, Shi-Joon;Jung, Eun-Ae;Kang, Jin-Kyu
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.222-222
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    • 2010
  • Transparent semiconductor oxide thin films have been attracting considerable attention as potential channel layers in thin film transistors (TFTs) owing to their several advantageous electrical and optical characteristics such as high mobility, high stability, and transparency. TFTs with ZnO or similar metal oxide semiconductor thin films as the active layer have already been developed for use in active matrix organic light emitting diode (AMOLED). Of late, there have been several reports on TFTs fabricated with InZnO, AlZnSnO, InGaZnO, or other metal oxide semiconductor thin films as the active channel layer. These newly developed TFTs were expected to have better electrical characteristics than ZnO TFTs. In fact, results of these investigations have shown that TFTs with the new multi-component material have excellent electrical properties. In this work, we present TFTs with inverted coplanar geometry and with a novel HfInZnO active layer co-sputtered at room temperature. These TFTs are meant for use in low voltage, battery-operated mobile and flexible devices. Overall, the TFTs showed good performance: the low sub-threshold swing was low and the $I_{on/off}$ ratio was high.

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핸즈프리 통신을 위한 다중채널 음성픽업 임베디드 시스템 설계 (A Design of Multi-channel Speech Pickup Embedded System for Hands-free Comuunication)

  • 주형준;박찬섭;전재국;김기만
    • 한국정보통신학회논문지
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    • 제11권2호
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    • pp.366-373
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    • 2007
  • 본 논문에서는 핸즈프리 음성 통신의 통화 품질 개선을 위해 ALTERA Nios-II 임베디드 프로세서를 이용하여 다중채널 음성 픽업 시스템을 구현하였다. 다중채널 음성 픽업 시스템은 zero-padding을 포함한 보간기를 갖는 지연-합 빔 형성기를 이용하였다. 구현된 음성 픽업 임베디드 시스템은 컴퓨터 시뮬레이션(MATLAB)과 범용 DSP 프로세서(TMS320C6711)을 이용하여 처리한 결과와 일치하였다. 구현된 방법은 비용과 설계시 간 측면에서 이전의 설계 방법들보다 효율적이다. 설계 결과로써 하드웨어의 LE(Logic Element)는 칩 상에서 3,649/5,980(61%)을 사용하였다.