• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.9-18
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• 2005

To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.12
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• pp.757-761
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• 2017

The computational fourier-transform moire (CFTM) method has been briefly explained and this method was used to perform strain analysis of a misfit dislocation in a strained $Si/Si_{0.55}Ge_{0.45}$ layer. An essential advantage of the CFTM method is that it does not require unwrapping, such that errors due to improper unwrapping can be excluded. The analysis results revealed that the Si layer was grown with tensile stress on $Si_{0.55}Ge_{0.45}$ and lattice constant of the Si layer along the growth direction was 1.9% smaller than that of $Si_{0.55}Ge_{0.45}$. On the other hand, strain of the misfit dislocation in the strained $Si/Si_{0.55}Ge_{0.45}$ layer was maximum at the dislocation core due to an extra half-plane and the $e_{xx}$ and $e_{yy}$ values were positive and negative, respectively, along the direction of a burgers vector.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.399-402
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• 2007

The effects of heat treatment on the electrical properties of strained-Si/SiGe-on-insulator (SGOI) devices were examined. We proposed the optimized heat treatment processes for improving the back interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA (rapid thermal annealing) before gate oxidation step and the post-RTA after source/drain dopant activation step, the electrical properties of strained-Si channel on $Si_{1-x}Ge_x$ layer were greatly improved, which resulting the improvement of the driving current, transconductance, and leakage current of SGOI-MOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• Korean Journal of Optics and Photonics
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• v.10 no.4
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• pp.306-310
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• 1999

Electron intersubband absorption in Sb $\delta$-doped Si(110)/SiGe multiple quantum well structures is observed. Normally incident light can excite electrons in Si(110) quantum wells, which is not possible for Si(001) or GaAs quantum wells. The influence of Ge composition in SiGe barries is investigated. As the Ge composition in SiGe barriers increases, the absorption strength is decreased and the transition energy is increased. It is verifired by comparing the calculated and experimental results obtained at various incident and polarization angles that normally incident light and parallel incident light are absorbed in different processes.

• ETRI Journal
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• v.28 no.2
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• pp.253-256
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• 2006

We propose a novel power metal oxide semiconductor field effect transistor (MOSFET) employing a strained-Si channel structure to improve the current drivability and on-resistance characteristic of the high-voltage MOSFET. A 20 nm thick strained-Si low field channel NMOSFET with a $0.75\;{\mu}m$ thick $Si_{0.8}Ge_{0.2}$ buffer layer improved the drive current by 20% with a 25% reduction in on-resistance compared with a conventional Si channel high-voltage NMOSFET, while suppressing the breakdown voltage and subthreshold slope characteristic degradation by 6% and 8%, respectively. Also, the strained-Si high-voltage NMOSFET improved the transconductance by 28% and 52% at the linear and saturation regimes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.9-16
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• 2005

The mobility in strained Si inversion layer on $Si_{1-x}Ge_x$ is calculated considering a quantum effect(subband energy and wavefunction) in inversion layer and relaxation time approximation. The quantum effect in inversion layer is obtained by using self-consistent calculation of $Schr\ddot{o}dinger$ and Poisson equations. For the relaxation time, intravalley and intervalley scatterings are considered. The result shows that the reason for the enhancement in mobility as Ge mole fraction increases is that the electron mobility in 2-폴드 valleys is about 3 times higher than that of 4-폴드 valleys and most electrons are located in 2-폴드 valleys as Ge mole fraction increases. Meanwhile, for the phonon-limited mobility the fitting to experimental data, Coulomb and surface roughness mobilities are included in total mobility, Deformation potentials are selected for the calculated effective field, temperature, and Ge mole fraction dependent mobilities to be fitted to experimental data, and then upgraded data can be obtained by considering nonparabolicity in Si band structure.

• Journal of the Korean Vacuum Society
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• v.16 no.2
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• pp.145-152
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• 2007

The evolution dynamics of nanoscale Ge islands on both Si (001) and (113) surfaces is explored using ultraviolet photoelectron emission microscopy (UV-PEEM). Real-time monitoring of the in-situ growth of the Ge island structures can allow us to study the variation of the size, the shape and the density of the nanostructures. For Ge depositions greater than ${\sim}4$ monolayer (ML) with a growth rate of ${\sim}0.4\;ML/min$ at temperatures of $450-550^{\circ}C$, we observed island nucleation on both surfaces indicating the transition from strained layer to island structure. During continuous deposition the circular islands grew larger via ripening processes. AFM measurements showed that the islands grown on Si (001) were dome-shaped while the islands on Si (113) were multiple-side faceted with flat tops of (113)-orientation. In contrast, for Ge deposition with a lower growth rate of ${\sim}0.15\;ML/min$ on Si(113), we observed the shape transition from circular into elongated island structures. The elongated islands grew longer along the [$33\bar{2}$] during continuous Ge deposition. The shape evolution of the islands is discussed in terms of strain relaxation and kinetic effects.

• Journal of the Korean Vacuum Society
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• v.8 no.2
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• pp.148-152
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• 1999

the low temperature magnetoresistance effect, electron mobilities, and 2 Dimensional electron Gases (2DEG) properties were investigated in $Si/Si_{1-x}Ge_x$ quantum well devices. N-type $Si/Si_{1-x}Ge_x$ structures were fabricated by utilizing a gas source Molecular Beam Epitaxy (GSMBE). Thermal oxidation was carried out in a dry O atmosphere at $700^{\circ}C$ for 7 hours. Electron mobilities were measured by using a Hall effect and a magnetoresistant effect at low temperatures down to 0.4K. Pronounced Shubnikov-de Haas (SdH) oscillations were observed at a low temperature showing two dimensional electron gases (2DEG) in s tensile strained Si quantum well. The electron sheet density (ns) of $1.5\times10^{12}[\textrm{cm}^{-2}]$ and corresponding electron mobility of 14200 $[\textrm{cm}^2V^{-1}s^{-1}]$ were obtained at a low temperature of 0.4K from $Si/Si_{1-x}Ge_x$ structures with thermally grown oxides.

• ETRI Journal
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• v.25 no.3
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• pp.203-209
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• 2003

This paper reports on our investigation of DC and RF characteristics of p-channel metal oxide semiconductor field effect transistors (pMOSFETs) with a compressively strained $Si_{0.8}Ge_{0.2}$ channel. Because of enhanced hole mobility in the $Si_{0.8}Ge_{0.2}$ buried layer, the $Si_{0.8}Ge_{0.2}$ pMOSFET showed improved DC and RF characteristics. We demonstrate that the 1/f noise in the $Si_{0.8}Ge_{0.2}$ pMOSFET was much lower than that in the all-Si counterpart, regardless of gate-oxide degradation by electrical stress. These results suggest that the $Si_{0.8}Ge_{0.2}$ pMOSFET is suitable for RF applications that require high speed and low 1/f noise.