• 한국정보통신학회논문지
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• 제26권5호
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• pp.682-687
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• 2022

터널링 전계효과 트랜지스터(tunneling field-effect transistor; TFET)로 적층된 3차원 적층형 집적회로(monolithic 3D integrated-circuit; M3DIC)에 대한 연구 결과를 소개한다. TFET는 MOSFET(metal-oxide-semiconductor field-effect transistor)와 달리 소스와 드레인이 비대칭 구조이므로 대칭구조인 MOSFET의 레이아웃과 다르게 설계된다. 비대칭 구조로 인해서 다양한 인버터 구조 및 레이아웃이 가능하고, 그 중에서 최소 금속선 레이어를 가지는 단순한 인버터 구조를 제안한다. 비대칭 구조의 TFET를 순차적으로 적층한 논리 게이트인 NAND 게이트, NOR 게이트 등의 M3DIC의 구조와 레이아웃을 제안된 인버터 구조를 바탕으로 제안한다. 소자와 회로 시뮬레이터를 이용해서 제안된 M3D 논리게이트의 전압전달특성 결과를 조사하고 각 논리 게이트의 동작을 검증한다. M3D 논리 게이트 별 셀 면적은 2차원 평면의 논리게이트에 비해서 약 50% 감소된다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.204.1-204.1
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• 2015

We studied the electrical properties and gate bias stress (GBS) stability of thin film transistors (TFTs) with multi-stacked InZnO layers. The InZnO TFTs were fabricated via solution process and the In:Zn molar ratio was 1:1. As the number of InZnO layers was increased, the mobility and the subthreshold swing (S.S) were improved, and the threshold voltage of TFT was reduced. The TFT with three-layered InZnO showed high mobility of $21.2cm^2/Vs$ and S.S of 0.54 V/decade compared the single-layered InZnO TFT with $4.6cm^2/Vs$ and 0.71 V/decade. The three-layered InZnO TFTs were relatively unstable under negative bias stress (NBS), but showed good stability under positive bias stress (PBS).

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.63.1-63.1
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• 2015

The next generation electronics need to not only be smaller but also be more flexible. To meet such demands, van der Waals (vdW) heterostructures using two dimensional (2D) atomic crystals such as graphene, hexagonal boron nitride (h-BN) and transition metal dichalcogenides (TMDCs) have been attracted intensely. In particular, for high performance of vdW heterostructures device, ultraclean interface between stacked 2D atomic crystals should be guaranteed. In this talk, I will present fabrication and characterization of the vdW field effect transistors toward performance enhancement by employing TMDCs channel, h-BN insulating layer and graphene electrode. Furthermore, it will also be introduced the characterization and surface engineering of graphene for gas molecule sensor.

• 한국정보통신학회논문지
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• 제24권5호
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• pp.682-685
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• 2020

In this paper, we analyze the dominant noise source of conventional inductively degenerated common-source (CS) cascode low noise amplifier (LNA) when width and gate length of stacked transistors vary. Analytical MOSFET and its noise model are used to estimate the contributions of noise sources. All parameters are based on measured data of 60nm, 90nm and 130nm CMOS devices. Based on the noise analysis for different frequencies and device parameters including process nodes, the dominant noise source can be analyzed to optimize noise figure on the configuration. We verified analytically that the intuctively degenerated CS topology can not sustain its benefits in noise above a certain operation frequency of LNA over different process nodes.

• 전자공학회논문지
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• 제50권1호
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• pp.174-179
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• 2013

이 논문에서는 multiple split ring resonator(MSRRs)와 로딩된 스위치드 제어부를 이용하여 2개의 전송영점을 가지는 대역통과 여파기를 설계하였다. 높은 선택도와 칩 사이즈의 초소형화를 위해 비대칭의 급전 선로를 도입하여 통과 대역 주위에 위치한 전송 영점 쌍을 생성하였다. Cross coupling 또는 source-load coupling 방식을 이용한 기존의 여파기와 비교해보면 이 논문에서 제안된 여파기는 단지 2개의 공진기만으로 전송 영점을 생성하여 높은 선택도를 얻었다. 여파기의 선택도와 민감도(삽입 손실)를 최적화하기 위해 비대칭 급전 선로의 위치에 따른 전송 영점과 삽입손실의 관계를 분석하였다. 통과 대역 주파수의 가변과 30dBm 정도의 고 출력 신호를 처리하기 위해 MSRRs의 최 외각 링에 MIM 커패시터와 stacked-FET으로 구성된 SOI-CMOS 스위치드 제어부가 로딩되어 있다. 스위칭 트랜지스터의 전원을 켜고 끔으로써 통과 대역 주파수를 4GHz로부터 5GHz까지 이동시킬 수 있다. 제안된 칩 여파기는 0.18-${\mu}m$ SOI CMOS 기술을 이용함으로써 높은 Q를 가지는 수동 소자와 stacked-FET의 집적을 가능하게 만들었다. 설계된 여파기는 $4mm{\times}2mm$ ($0.177{\lambda}g{\times}0.088{\lambda}g$)의 초소형화 된 크기를 가진다. 여기서 ${\lambda}g$는 중심 주파수에서의 $50{\Omega}$ 마이크로스트립 선로의 관내 파장을 나타낸다. 측정된 삽입손실(S21)은 5.4GHz, 4.5GHz에서 각 각 5.1dB, 6.9dB를 나타내었다. 설계된 여파기는 중심 주파수로부터 500MHz의 오프셋에서 20dB이상의 대역외 저지 특성을 나타내었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.230-238
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• 2017

We have proposed an InGaAs-based gate-all-around (GAA) tunneling field-effect transistor (TFET) with a stacked dual-metal gate (DMG). The electrical performances of the proposed TFET are evaluated through technology computer-aided design (TCAD) simulations. The simulation results show that the proposed TFET demonstrates improved DC performances including high on-state current ($I_{on}$) and steep subthreshold swing (S), in comparison with a single-metal gate (SMG) TFET with higher gate metal workfunction, as it has a thinner source-channel tunneling barrier width by low workfunction of source-side channel gate. The effects of the gate workfunction on $I_{on}$, the off-state current ($I_{off}$), and S in the DMG-TFETs are examined. The DMG-TFETs with PNPN structure demonstrate outstanding DC performances and RF characteristics with a higher n-type doping concentration in the $In_{0.8}Ga_{0.2}As$ source-side channel region.

• 한국컴퓨터산업학회논문지
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• 제6권5호
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 전기전자학회논문지
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• 제16권3호
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• 전자공학회논문지
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• 제50권12호
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• pp.49-55
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• 2013

초음파 의료 영상 응용 분야를 위한 고전압 고집적 아날로그 front-end 집적회로를 0.18-${\mu}m$ 표준 CMOS 반도체 공정을 이용하여 구현하였다. 제안 된 아날로그 front-end 집적회로는 2.6 MHz에서 15 Vp-p 전압까지 동작하는 트랜지스터 stacking구조를 이용한 고전압 펄서와, 저전압에서 동작하는 저잡음 transimpedance 증폭기, 그리고 송신부와 수신부의 분리를 위한 고전압 차단 스위치로 구성되어 있다. 설계 된 집적회로는 $0.15mm^2$ 이하의 작은 면적을 사용함으로써 휴대용 영상 시스템을 포함한 다중 어레이 초음파 의료 영상 시스템에 적용이 가능하다.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.