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http://dx.doi.org/10.4313/JKEM.2002.15.10.831

High Density and Low Voltage Programmable Scaled SONOS Nonvolatile Memory for the Byte and Flash-Erased Type EEPROMs  

김병철 (진주산업대학교 전자공학과)
서광열 (광운대학교 반도체 및 신소재공학과)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.15, no.10, 2002 , pp. 831-837 More about this Journal
Abstract
Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.
Keywords
SONOS; Charge trap type; Byte-erased type EEPROM; Flash-erased type EEPROM; 3 V single power supply;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
연도 인용수 순위
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