• Proceedings of the IEEK Conference
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• summer
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• pp.77-81
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• 2004

In this paper, we propose a analog front-end (AFE) for noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection. The proposed AFE are designed using 0.18 micron CMOS technology and verified by simulation using SPICE. The proposed AFE consist of Sample-and-Hold block, Analog-to-Digital converter, synchronizer, delayed clock generator and impulse generator. The time resolution of 1ns is obtained with 100MHz system clocks and the synchronized 10-bit digital outputs are delivered to the baseband. The impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results show the feasibility of the proposed UWB AFE systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.1-8
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• 2006

In this paper, we designed a pixel circuit for AMOLED display based on organic thin film transistors and analyzed the operation with SPICE simulation. First, we theoretically designed the pixel circuit with the result of layout for fabricating $32\times32$ AMOLED panel, TFT W/L and capacitance of storage capacitor. And we simulated the designed pixel circuit using HSPICE for analyzing electrical performance. As a result of simulation, we identified the possibility of AMOLED display based on OTFTs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2000-2003
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• 2002

In this paper, an IC chip of a cell- network type circuit constructed with 1-dimensional chaos circuits is reported. The circuit, is designed by sing switched-current (Sl) techniques. In the proposed circuit, by controlling connections of cells, an S- dimensional circuit (S ＝ 1, 2, 3,…) and a synchronization system can be constructed easily. Furthermore, in spite of faults of a few cells, the circuit can reconstruct above-mentioned systems only to change connections of cells. This feature will open up new vista for engineering applications which are used in a distance place such as space, deep sea, etc. since it is difficult to repair faults of these application systems. To investigate the characteristics of the circuit, SPICE simulations are performed. The VLSI chip is fabricated from the layout design using a CAD tool, MAGIC. The proposed circuit is integrable by a standard 1.2 $\mu\textrm{m}$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.497-505
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• 2016

The two-dimensional (2D) Discrete Cosine Transform (DCT) is used widely in image and video processing systems. The perception of human visualization permits us to design approximate rather than exact DCT. In this paper, we propose a digital implementation of 16-point approximate 2D DCT architecture based on one-dimensional (1D) DCT and Modified Gate Diffusion Input (MGDI) technique. The 8-point 1D Approximate DCT architecture requires only 12 additions for realization in digital VLSI. Additions can be performed using the proposed 8 transistor (8T) MGDI Full Adder which reduces 2 transistors than the existing 10 transistor (10T) MGDI Full Adder. The Approximate MGDI 2D DCT using 8T MGDI Full adders is simulated in Tanner SPICE for $0.18{\mu}m$ CMOS process technology at 100MHZ.The simulation result shows that 13.9% of area and 15.08 % of power is reduced in the 8-point approximate 2D DCT, 10.63 % of area and 15.48% of power is reduced in case of 16-point approximate 2D DCT using 8 Transistor MGDI Full Adder than 10 Transistor MGDI Full Adder. The proposed architecture enhances results in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.463-470
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• 2014

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.197-201
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• 1997

To realize 10-Gbit/s optical transmission systems, we designed and fabricated a limiting amplifier with extremely high operation frequencies over 10-GHz using AlGaAs/GaAs heterojunction bipolar transistors (HBTs), and investigated their performances. Circuit design and simulation were performed using SPICE and LABRA. A discrete AlGaAs/GaAs HBT with the emitter area of 1.5${\times}$10$\mu\textrm{m}$$^2$, used for the circuit fabrication, exhibited the cutoff frequency of 63GHz and maximum oscillation frequency of 50GHz. After fabrication of MMICs, we observed the very wide bandwidth of DC∼15GHz for a limiting amplifier from the on-wafer measurement. Ceramic-packaged limiting amplifier showed the excellent eye opening, the output voltage swing of 750mV\ulcorner, and the rise/fall time of 40ps, measured at the data rates of 10-Gbit/s.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.46-52
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• 1994

DC and AC current crowding effects for microwave and high speed bipolar transistors are investigated in detail using a new and accurate measurement technique based on Z-parameter equationa. Using the new measurement technique dc and ac current crowding effects have been explained clearly in bipolar junction transistors. To model ac crowding effects a capacitive element defined as base capacitance (C$_b$), called ac crowding capacitance is added to base resistance in parallel thereby treating the base resistance(R$_b$) as base impedance Z$_b$. It is shown that base resistance decreases with increasing collector current due to dc current crowding and approaches to a certain limited value at high collector current due to current crowding and approaches to a certain limited value at high collector currents regardless of the emitter size. It is also observed that due to ac current crowding base capacitance increases with increasing collector current. To quantigy the ac crowding effects for SPICE circuit simulation the base capacitance(C$_b$) including the base depletion and diffusion components has been modeled with an analytical expression form.

• Korean Journal of Food Science and Technology
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• v.35 no.2
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• pp.316-319
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• 2003

Titratable acidity, pH, color, and pungency characteristics of commercial kimchi were investigated. Titratable acidity and of pH commercial kimchi waried significantly from pH 3.88 and titratable acidity 0.28% in non-fermented kimchi, to pH 6.20 and titratable acidity 1.13% in over-fermented one. Capsaicinoid contents of kimchi showed low pungency intensity of 0.18% to strong pungency intensity of 2.02, and American spice trading association value of kimchi samples ranged $0.52{\sim}4.1$.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.11
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• pp.1227-1232
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• 2014

This paper relates 10% shrink from $0.13{\mu}m$ design for core devices as well as input and output (I/O) devices different from previous poly length shrink size only. We analyzed body effect with different channel length and doping profile simulation. After fixing the gate oxide module process, LDD implant conditions were optimized such as decoupled plasma nitridation of gate oxide, TEOS oxide $100{\AA}$ before LDD implant and 22o tilt-angle(45o twist-angle) LDD implant respectively to match the spice DC parameters of pre-shrink and finally matched them within 5%.