• 센서학회지
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• 제24권6호
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• pp.359-363
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• 2015

This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $2^n$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.

• 전자공학회논문지
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• 제50권11호
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• pp.64-69
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• 2013

본 논문에서는 10-bit 해상도의 Two-Step Single-Slope A/D 변환기를 이용한 고속 CMOS Image Sensor(CIS)를 제안하였다. 제안하는 A/D 변환기는 5-bit coarse ADC 와 6-bit fine ADC 로 구성되어 있으며, 기존의 Single-Slope A/D 변환기보다 10배 이상의 변환속도를 나타내었다. 또한 고속 동작에서 적은 노이즈 특성을 갖기 위해 Digital Correlated Double Sampling(D-CDS) 회로를 제안하였다. 설계된 A/D 변환기는 0.13um 1-poly 4-metal CIS 공정으로 제작되었으며 QVGA($320{\times}240$)급 해상도를 갖는다. 제작된 칩의 유효면적은 $5mm{\times}3mm$ 이며 3.3V 전원전압에서 약 35mW의 전력소모를 나타내었다. 변환속도는 10us 이었으며, 프레임율은 220 frames/s으로 측정되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• 대한전자공학회논문지SD
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• 제48권2호
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• pp.20-27
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• 2011

모바일 기기에 장착되는 CMOS 이미지 센서(CIS) 칩은 배터리 용량의 한계로 인해 저전력 소모를 요구한다. 본 논문에서는 전력소모를 줄일 수 있는 데이터 플립플롭 회로와 새로운 저전력 구조의 Single-Slope A/D Converter(SS-ADC)를 사용한 이미지 센서를 설계하여 모바일 기기에 사용되는 CIS 칩의 전력 소모를 감소시켰다. 제안하는 CIS는 $2.25um{\times}2.25um$ 면적을 갖는 4-Tr Active Pixel Sensor 구조를 사용하여 QVGA($320{\times}240$)급 해상도를 갖도록 설계되었으며 0.13um CMOS 공정에서 설계되었다. 실험 결과, CIS 칩 내부의 SS-ADC 는 10-b 해상도를 가지며, 동작속도는 16 frame/s 를 만족하였고, 전원 전압 3.3V(아날로그)/1.8V(Digital)에서 25mW의 전력 소모를 보였다. 측정결과로부터 제안된 CIS 칩은 기존 CIS 칩에 비해 대기시간동안 약 22%, 동작시간동안 약 20%의 전력이 감소되었다.

• 센서학회지
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• 제24권4호
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• pp.252-257
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• 2015

This paper proposes a single slope A/D converter (SSADC) that is possible to process the signal of the ultraviolet, visible and infrared rays with a single chip. And the proposed SSADC is a type of single channel ADC. In the conventional SSADC, it is possible to process the only one signal with a kind of the sensor because the speed of the operating frequency and the slope of ramp signal generated by the ramp generator are fixed. In order to improve the disadvantages, a ramp generator which has variable slope in ramp function is designed and $3{\times}1$ MUX(multiplexer) is adopted so that we can change the speed of the operating frequency and the slope of ramp signal. Therefore, the multiple signal processing of the wanted sensors can be possible. The designed circuit is layout by the $0.35-{\mu}m$ CMOS 2-poly 4-metal technology process and is checked through DRC and LVS tools.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.335-337
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• 1993

Offset voltage and drift characteristics of operational amplifier are critical factor to precision AID conversion System. In this study, a method is suggested to design the programmable A/D conversion system which has high resolution and low drift characteristics. First, hardware was designed to reduce the offset voltage of integrator and comparator, and analog switches are connected to reduce the drift characteristics of operational amplifier. And then, a calibration software technique was performed to obtain the stable data from A/D converter. The main advantage of our method is high precision A/D converter can be constructed with low cost and high confidence. Therefore proposed method is expected to be used in the industrial field where a high precision measurement is required.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.104-110
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• 2011

A CMOS Image Sensor (CIS) mounted on mobile appliances requires low power consumption due to limitations of the battery life cycle. In order to reduce the power consumption of CIS, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination and a low power single slope analog-to-digital (A/D) converter with a sleep-mode comparator. Based on 0.13 ${\mu}m$ CMOS process, the chip satisfies QVGA resolution (320 ${\times}$ 240 pixels) that the cell pitch is 2.25 um and the structure is a 4-Tr active pixel sensor. From the experimental results, the performance of the CIS has a 10-b resolution, the operating speed of the CIS is 16 frame/s, and the power dissipation is 25 mW at a 3.3 V(analog)/1.8 V(digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption was reduced by approximately 22% in the sleep mode, and 20% in the active mode.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 B
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• pp.693-696
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• 1999

This paper describes a new voltage recorder for the voltage management of a power distribution line by using a new voltage measurement technique. The RMS(Root Mean Square) voltage measurement for the power line under the assumption of a sinusoidal input voltage is taken by the full-wave rectifier, half-adder utilizing operational amplifier(OP) circuit. A/D converter utilizing a dual slope converter converts an analog voltage signal into a serial pulse. The pulse is counted with a single chip micro-controller, converted with the RMS voltage, and saved into a flash memory. In the last, a new voltage recorder with compact size and multifunction is developed. Also, Voltage Management System that can analyze the stored data via RS-232C cable is developed based on Windows 95 and Visual C++.

• 대한전자공학회논문지SD
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• 제43권1호
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• pp.65-70
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• 2006

인간의 눈은 넓은 영역의 빛의 밝기를 받아들이기 위해 log 응답 특성을 갖는 반면 이미지 센서는 제한된 dynamic range를 갖는다. 선형 ADC(analog-to-digital converter)를 적용한 일반적인 CMOS 이미지 센서는 이미지의 어두운 부분을 확실하게 나타나게 하기 위하여 이득을 높이며 일부 밝은 부분의 포화 현상을 막을 수는 없다. 감마 보정은 인간의 눈의 반응에 맞추는 본질적인 방법이다. 그러나 디지털 감마 보정은 ADC 해상도와 센서 자체의 dynamic range의 한계 때문에 이미지의 질을 떨어뜨린다. 본 논문은 아날로그 감마 보정을 수행하는 비선형 ADC를 사용한 CMOS 이미지 센서를 제안한다. 제안된 비선형 ADC를 적용한 CMOS 이미지 센서는 $0.35{\mu}m$ CMOS 공정을 이용하였다. 제안된 비선형 ADC CIS를 적용한 아날로그 감마 보정이 기존의 디지털 감마 보정 방법에 비해 질적으로 향상된 이미지를 보였는데 수치적으로 200mV 미만 픽셀 출력으로 이루어진 저조도 이미지에서의 peak-signal-to-noise ratio (PSNR)는 제안된 아날로그 감마 보정이 27.8dB, 디지털 감마 보정이 25.6dB로 측정되어 아날로그 감마 보정이 디지털 감마 보정에 비해 저조도 양자화 잡음을 $28.8\%$ 개선되었음을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.