1 |
sensor with column-to-column FPN reduction."in Proc. IEEE ISSCC Dig. Tech. Papers, pp. 108-109, 450, Feb. 2000.
|
2 |
S. Lim, J. Cheon, S. Ham, and G. Han, "A new correlated double sampling and single slope ADC circuit for CMOS image sensors,"in Proc. Int. SoC Des. Conf., pp. 129-131, Oct. 2004.
|
3 |
M. F. Snoeij et al., "Multiple-ramp column-parallel ADC architectures for CMOS image sensors," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2968-2967, Dec. 2007.
DOI
ScienceOn
|
4 |
J. Lee, S. Lim, and G. Han, "A 10 b column-wise two-stage single-slope ADC for high-speed CMOS image sensor," in Proc. IEEE Int. Image Sensor Workshop, pp. 196-199, Jun. 2007.
|
5 |
Y. Nitta et al., "High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor," ISSCC Dig. Tech. Papers, pp. 500-501, Feb. 2006.
|
6 |
Y. Yoshihara et al. "A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor with seamless mode change," IEEE J. Solid-State Circuits, vol. 41, pp.2998-3006 Dec. 2006.
DOI
ScienceOn
|
7 |
M. F. Snoeij, et al, "A CMOS imager with column-level ADC using dynamic column fixed-pattern noise reduction," IEEE J. Solid-State Circuits, vol. 41, pp. 3007-3015, Dec. 2006.
DOI
ScienceOn
|
8 |
S. Lim, J. Lee, G. Han, "A high-Speed CMOS image sensor with Column-parallel Two-Step Single-Slope ADCs."in Proc. IEEE J. Solid-State Circuits, Vol. 56, no. 3 pp.393-398, Mar. 2009.
|
9 |
I. Takayanagi, J. Nakamura, "High-resolution CMOS Video Image Sensors," Proceeding of the IEEE, Vol. 101, pp.61-73, Jan. 2013.
DOI
ScienceOn
|