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Design of a CMOS Image Sensor Based on a Low Power Single-Slope ADC  

Kwon, Hyuk-Bin (Dept, of Semiconductor Science, Dongguk Univ.)
Kim, Dae-Yun (Dept, of Semiconductor Science, Dongguk Univ.)
Song, Min-Kyu (Dept, of Semiconductor Science, Dongguk Univ.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.2, 2011 , pp. 20-27 More about this Journal
Abstract
A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.
Keywords
CMOS Image Sensor; mobile appliances; data flip-flop; Single-slope analog-to-digital converter; QVGA resolution;
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Times Cited By KSCI : 1  (Citation Analysis)
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