JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design and Evaluation of a CMOS Image Sensor with Dual-CDS and Column-parallel SS-ADCs

  • Um, Bu-Yong (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kim, Jong-Ryul (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kim, Sang-Hoon (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Lee, Jae-Hoon (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Cheon, Jimin (School of Electronic Engineering, Kumoh National Institute of Technology) ;
  • Choi, Jaehyuk (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Chun, Jung-Hoon (College of Information & Communication Engineering, Sungkyunkwan University)
  • Received : 2016.03.11
  • Accepted : 2016.08.28
  • Published : 2017.02.28
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Abstract

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

Keywords

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