• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.164-169
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• 2008

The effects of the antisite related defects on the electronic structure of silica and the gate leakage current have been investigated using first-principles calculations. Energy levels related to the antisite defects in silicon dioxide have been introduced into the bandgap, which are nearly 2.0 eV from the top of the valence band. Combining with the electronic structures calculated from first-principles simulations, tunneling currents through the silica layer with antisite defects have been calculated. The tunneling current calculations show that the hole tunneling currents assisted by the antisite defects will be dominant at low oxide field whereas the electron direct tunneling current will be dominant at high oxide field. With increased thickness of the defect layer, the threshold point where the hole tunneling current assisted by antisite defects in silica is equal to the electron direct tunneling current extends to higher oxide field.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.83-90
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• 1998

The effects of dopant activation anneal on GOI (Gate Oxide Integrity) of MOS capacitor with amorphous silicon gate electrode were investigated. It was found that the amorphous silicon gate electrode was crystallized and the dopant atoms were sufficiently activated by activation anneal. The mechanical stress of gate electrode that reveals large compressive stress in amorphous state, was released with increase of anneal temperature from $700^{\circ}C$ to 90$0^{\circ}C$. The resistivity of gate electrode polycrystalline silicon film is decreased by the increase of anneal temperature. The reliability of thin gate oxide and interface properties between oxide and silicon substrate greatly depends on the activation anneal temperature. The charge trapping characteristics as well as oxide reliability are improved by the anneal of 90$0^{\circ}C$ compare to that of $700^{\circ}C$ or 80$0^{\circ}C$. Especially, the lifetimes of the thin gate oxide estimated by TDDB method is 3$\times$10$^{10}$ for the case of $700^{\circ}C$ anneal, is significantly increased to 2$\times$10$^{12}$ for the case of 90$0^{\circ}C$ anneal. Finally, the interface trap density is reduced with relaxation of mechanical stress of gate electrode.

• Journal of the Korean Vacuum Society
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• v.3 no.1
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• pp.71-76
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• 1994

The electrical characteristics of the capacitor dielectric films of amorphous silicon-nit-ride-oxide(ANO) structures are compared with the capacitor dielectric films of oxide-nitride-oxide (ONO) structrues The electrical characteristics of ONO and ANO films were evaluated by high frequency(1 MHz) C-V high frequency C-V after constant voltage stree I-V TDDB and refresh time measurements. ANO films shows good electrical characteristics such as higher total charge to breakdown storage capacitance and longer refresh time than ONO films. Also it makes little difference that leakage current and flat band voltage shyift(ΔVfb)of ANO ana ONO films.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.687-688
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• 2009

• Journal of Convergence for Information Technology
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• v.7 no.5
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• pp.123-128
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• 2017

Nanostructured materials have received attention due to their unique electronic, optical, optoelectrical, and magnetic properties as a results of their large surface-to-volume ratio and quantum confinement effects. Thermal chemical vapor deposition process has attracted much attention due to the synthesis capability of various structured nanomaterials during the growth of nanostructures. In this study, silicon oxide nanowires were grown on Si\$SiO_2$(300 nm)\Pt(5~40 nm) substrates by two-zone thermal chemical vapor deposition with the source material $TiO_2$ powder via vapor-liquid-solid process. The morphology and crystallographic properties of the grown silicon oxide nanowires were characterized by field-emission scanning electron microscope and transmission electron microscope. As results of analysis, the morphology, diameter and length, of the grown silicon oxide nanowires are depend on the thickness of the catalyst films. The grown silicon oxide nanowires exhibit amorphous phase.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.3
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• pp.233-240
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• 2023

p-type Tunnel Oxide Passivating Contacts (TOPCon) solar cell is fabricated with a poly-Si/SiO_x structure. It simultaneously achieves surface passivation and enhances the carriers' selective collection, which is a promising technology for conventional solar cells. The quality of passivation is depended on the quality of the tunnel oxide layer at the interface with the c-Si wafer, which is affected by the bond of SiO formed during the subsequent annealing process. The highest cell efficiency reported to date for the laboratory scale has increased to 26.1%, fabricated by the Institute for Solar Energy Research. The cells used a p-type float zone silicon with an interdigitated back contact (IBC) structure that fabricates poly-Si and SiO_x layer achieves the highest implied open-circuit voltage (iV_oc) is 750 mV, and the highest level of edge passivation is 40%. This review presents an overview of p-type TOPCon technologies, including the ultra-thin silicon oxide layer (SiO_x) and poly-silicon layer (poly-Si), as well as the advancement of the SiO_x and poly-Si layers. Subsequently, the limitations of improving efficiency are discussed in detail. Consequently, it is expected to provide a basis for the simplification of industrial mass production.

• Transactions on Electrical and Electronic Materials
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• v.16 no.6
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.106-114
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• 1994

The local oxidation of silicon (LOCOS) technology, which uses a silicon nitride film as an oxidation mask and a pad oxide beween the silicon nitride and the silicon substrate, has been widely used in integrated circuits for process simplicity. But, due to long brid's beak length, there are difficulties in scabilities. Many advanced isolation techniques have been wuggested for the feduction of bird's beak length. In this paper, we presented reduced bird's beak length using the polybuffered oxide and the silicon nitride as the sidewall. Also, investigating the electrical behavior of the parasitic Al-gate MOSFET on LOCOS, we proved the validity for new isolation process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.4
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• pp.439-444
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• 2024

This study investigates the post-thermal treatment effects on the efficiency of silicon heterojunction solar cells, specifically examining the influence of annealing on p-type microcrystalline silicon oxide and ITO thin films. By assessing changes in carrier concentration, mobility, resistivity, transmittance, and optical bandgap, we identified conditions that optimize these properties. Results reveal that appropriate annealing significantly enhances the fill factor and current density, leading to a notable improvement in overall solar cell efficiency. This research advances our understanding of thermal processing in silicon-based photovoltaics and provides valuable insights into the optimization of production techniques to maximize the performance of solar cells.