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http://dx.doi.org/10.4313/TEEM.2015.16.6.312

Use of Hard Mask for Finer (<10 μm) Through Silicon Vias (TSVs) Etching  

Choi, Somang (Department of Electrical Engineering, Myongji University)
Hong, Sang Jeen (Department of Electrical Engineering, Myongji University)
Publication Information
Transactions on Electrical and Electronic Materials / v.16, no.6, 2015 , pp. 312-316 More about this Journal
Abstract
Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.
Keywords
Through silicon via; Plasma etch;
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