• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

• 한국신재생에너지학회:학술대회논문집
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• 2009.06a
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• pp.126-129
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• 2009

In this study, it was aimed to develop the re-use technology of ultra-fine silicon powders, by-products during the current production process of high purity poly-Si feedstock. For this goal, the compacts of the silicon powders were tried to fabricate by CIP (Cold Isostatic Pressing) method using silicon rubber mold without chemical binder materials. The density ratio of the silicon powder compacts reached 74%. In order to simulate the actual handling and charging conditions of feedstock material in casting process, a shaking test was carried out and mass loss measured. Finally, the silicon powder compacts were melted using a cold crucible induction melting method and the purity assessment was conducted by Hall effect measurement.

• KIEE International Transactions on Electrophysics and Applications
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• v.2C no.5
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• pp.258-261
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• 2002

Electrical forming dependent current-voltage (I-V) and numerically derived differential conductance(dI／dV) characteristics have been presented in the multi-layer nano-crystalline silicon／oxygen (no-Si／O) superlattice. Distinct staircase-like features, indicating the presence of resonant tunnel barriers, are clearly observed in the dc I-V characteristics. Also, all samples showed a continuous change in current and zero conductivity around OV corresponding to the Coulomb blockade in the calculated dI／dV-V curve. Also, Ra-man scattering measurement showed the presence of a nano-crystalline Si structure. This result becomes a step in the right direction for the fabrication of silicon-based optoelectronic and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in high speed and low power silicon MOSFET devices of the future.

• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.264-267
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• 2007

It is important to reduce optical losses from front surface reflection to improve the efficiency of crystalline silicon solar cells. Surface texturing by isotropic etching with acid solution based on HF and $HNO_3$ is one of the promising methods that can reduce surface reflectance. Anisotropic texturing with alkali solution is not suitable for multicrystalline silicon wafers because of its various grain orientations. In this paper, we textured multicrystalline silicon wafers by simple wet chemical etching using acid solution to reduce front surface reflectance. After that, surface morphology of textured wafer was observed by Scanning Electron Microscope(SEM) and Atomic Force Microscope(AFM), surface reflectance was measured in wavelength from 400nm to 1000nm. We obtained 29.29% surface reflectance by isotropic texturing with acid solution in wavelength from 400nm to 1000nm for fabrication of multicrystalline silicon solar cells.

• Journal of the Korean Ceramic Society
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• v.42 no.10 s.281
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• pp.645-648
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• 2005

To fabricate a (100) silicon hard master, we used anisotropic wet etching for the embossing. The etching chemical for the sili­con wafer was a TMAH 25$\%$ solution. The anisotropic wet etching produces a smooth sidewall surface inclined at 54.7°, and the surface roughness of the fabricated master is about 1 nm. After spin coating an organic-inorganic sol-gel hybrid resin on a silicon substrate, we used the fabricated master to form patterns on the silicon substrate. Thus, we successfully obtained patterns via the hot embossing technique with the (100) silicon hard master. Moreover, by using a single hydrophobic surface treatment of the master, we succeeded in achieving uniform surface roughness of the embossed patterns for more than ten embossments.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.121-124
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• 2004

The research on the porous silicon having low wafer stress during the oxidation process in IPOS(Isolation by Porous Oxidized Silicon) were carried out. Fine pores with less than 100A of diameter were found in the porous silicon which from p-type Si by electrochemical etching. In this study, it is possible to make the porous silicon with 59% of porosity.

• Journal of Integrative Natural Science
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• v.7 no.4
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• pp.221-226
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• 2014

Optically encoded porous silicon smart particles were successfully fabricated from the free-standing porous silicon thin films using ultrasono-method. DBR PSi was prepared by an electrochemical etch of heavily doped $p^{{+}{+}}$-type silicon wafer. DBR PSi was prepared by using a periodic pseudo-square wave current. The surface-modified DBR PSi was prepared by either thermal oxidation or thermal hydrosilylation. Free-standing DBR PSi films were generated by lift-off from the silicon wafer substrate using an electropolishing current. Free-standing DBR PSi films were ultrasonicated to create DBR-structured porous smart particles. Optical characteristics of porous smart particles were measured by FT-IR spectroscopy. The surface morphology of porous smart particles was determined by FE-SEM.

• Proceedings of the Korean Vacuum Society Conference
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• 2002.02a
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• pp.106-106
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• 2002

• Journal of Sensor Science and Technology
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• v.11 no.1
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• pp.1-8
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• 2002

In this paper, a thermopile which is applied to wide uses of temperature measuring was fabricated and its characteristic was improved by appling SOI structure to the fabrication. We improved characteristic of the thermopile by using single crystal silicon strips that has high seebeck coefficient and dielectric isolating the silicon strips from substrate with silicon dioxide film which dramatically decrease thermal conductivity between hot and cold junction compared to a silicon strip which was fabricated by ion implantation. The thermopile consists of 17 p-type single crystal silicon strips and 17 n-types by serial connection. The result of electromotive force measuring showed very good characteristic as 130mV/K when temperature difference between the two ends of the thermopile occurs by applying light on the thermopile fabricated with silicon strips of $1600{\mu}m$ length, $40{\mu}m$ width, $1{\mu}m$ thickness.

• 한국태양에너지학회:학술대회논문집
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• 2011.11a
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• pp.154-157
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• 2011

Hydrogenated silicon nitride deposited by LF-PECVD is commonly used for anti-reflection coating and passivation in silicon solar cell fabrication. The deposition of the optimized silicon nitride on the surface is elemental in crystalline silicon solar cell. In this work, the carrier lifetimes were measured while the thicknesses of $SiN_x$ were changed from 700 ${\AA}$ to 1150 ${\AA}$ with the gas flow of $SiH_4$ as 40 sccm and $NH_3$ as 120 sccm,. The carrier lifetime enhanced as the thickness of $SiN_x$ increased due to improved passivation effect. To study the characteristics of $SiN_x$ with various gas ratios, the gas flow of $NH_3$ was changed from 40 sccm to 200 sccm with intervals of 40 sccm. The thickness of $SiN_x$ was fixed as 1000 ${\AA}$ and the gas flow of $SiH_4$ as 40 sccm. The refractive index of SiNx and the carrier lifetime were measured before and after heat treating at $650^{\circ}C$ to investigate their change by the firing process in solar cell fabrication. The index of refraction of SiNx decreased as the gas ratios increased and the longest carrier lifetime was measured with the gas ratio $NH_3/SiH_4$ of 3.