• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2004년도 추계학술대회 논문집
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• pp.463-467
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• 2004

This paper presents the fabrication possibility of the micro actuator which uses a micro-thermal bubble, generated b micro-heater under pulse heating. The valve-less micropump using the diffuser/nozzle is consists of the lower plate, he middle plate, the upper plate. The lower plate includes the channel and chamber are fabricated on high processability silicon wafer by the DRIE(Deep Reactive Ion Etching) process. The middle plate includes the chamber and diaphragm d the upper plate is the micro-heater. The Micropump is fabricated by bonding process of the three layer. This paper resented the possibility of the PCR chip operation by the fabricated micropump.

• 정보저장시스템학회논문집
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• 제1권2호
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• pp.175-181
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• 2005

SiOB is an essential part of slim optical pickup, where the silicon mirror, LD stand, silicon PD are integrated and LD is flip chip bonded. SiOB is fabricated with bulk micromachining. Especially the fabrication of silicon wafer with stepped concave areas has many extraordinary difficulties. As a matter of fact, experiences and knowledges are rare in the fabrication of the highly stepped silicon wafer. The difficulties occurring in the integration of PD and SiOB, and highly stepped patterning, and silicon mirror roughness and how-to-solve will be discussed.

• 센서학회지
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• 제14권5호
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• pp.357-361
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• 2005

Low-stress silicon nitride (LSN) thin films with embedded metal line have been developed as free standing structures to keep microspheres in proper locations and localized heat source for application to a chip-based sensor array for the simultaneous and near-real-time detection of multiple analytes in solution. The LSN film has been utilized as a structural material as well as a hard mask layer for wet anisotropic etching of silicon. The LSN was deposited by LPCVD (Low Pressure Chemical Vapor Deposition) process by varing the ratio of source gas flows. The residual stress of the LSN film was measured by laser curvature method. The residual stress of the LSN film is 6 times lower than that of the stoichiometric silicon nitride film. The test results showed that not only the LSN film but also the stack of LSN layers with embedded metal line could stand without notable deflection.

• 수산해양교육연구
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• 제20권3호
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• pp.410-415
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• 2008

To evaluate the performance of nucleate boiling heat transfer between a plain and micro-fin surfaces, the experimental tests have been carried out under various conditions with fluorinert liquid FC-72, which is chemically and electrically stable. Two kinds of micro fins with the dimensions of $200{{\mu}m}{\times}20{{\mu}m}$ and $100{{\mu}m}{\times}10{{\mu}m}$ (width x height) were fabricated on the surface of a silicon chip. The experiments were performed on the liquid subcooling of 5, 10 and 20K under the atmospheric condition. The presented data showed a similar trend in the comparison with result of Rainey & You. Due to its expanded surface areas, the heat flux properties has been significantly enhanced on micro-fin surface comparing to the plain surface.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.1-6
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• 2002

A new closed-form expressions to calculate frequency-dependent distributed inductance and the associated distributed series resistance of single interconnect on a lossy silicon substrate (CMOS technology) are presented. The proposed analytic model for series impedance is based on a self-consistent field method and the vector magnetic potential equation. It is shown that the calculated frequency-dependent distributed inductance and the associated resistance are in good agreement with the results obtained from rigorous full wave solutions and CAD-oriented equivalent-circuit modeling approach.

• 전자공학회논문지A
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• 제29A권9호
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• pp.76-84
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• 1992

The DSP silicon compiler consists of language compiler, module generator, placement tool, router, layout generation tools, and simulator. In this paper, The language compiler, the module generator, placement tool, and simulator were developed and provided for the system designer. The language compiler translates the designer's system description language into the intermediate form file. The intermediate form file expresses the interconnections and specifications of the cells in the cell library. The simulator was developed and provided for the behavioral verification of the DSP system. For its implementation, the event-driven technique and the C$^{++}$ task library was used. The module generator was developed for the layout of the verified DSP system, and generates the functional block to be used in the DSP chip. And then the placement tool determines the appropriate positions of the cells in the DSP chip. In this paper, the placement tool was implemented by Min-Cut and Simulated Annealing algorithm. The placement process can be controlled by the several conditions input by the system designer.

• 대한금속재료학회지
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• 제48권6호
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• pp.557-564
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• 2010

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

• 전기전자학회논문지
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• 제1권1호
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• pp.1-10
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• 1997

It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.

• 대한기계학회논문집B
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• 제30권10호
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• pp.957-965
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• 2006

A high-performance hot chuck is designed as a heating device for an ultra-precision flip-chip bonder with infrared alignment system. Analysis of design requirements for thermal performance leads to a radiative heating mechanism employing two halogen lamps as heating source. The heating tool is made of silicon carbide characterized by high thermal diffusivity and small thermal expansion coefficient. Experimental tests are performed to assess heat-up performance and temperature uniformity of the heating tool. It is revealed that the initial design of hot chuck results in a good heat-up speed but there exist a couple of troubles associated with control and integrity of the device. As a means to resolve the raised issues, a revised version of heating tool is proposed, which consists of a working plate made of silicon carbide and a supporting structure made of stainless steel. The advantages of this two-body heating tool are discussed and the improved features are verified experimentally.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.83-87
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• 2004

Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.