• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2649-2655
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• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.405-408
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• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure, which is a type of an IIR filter. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.2
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• pp.111-117
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• 2004

The low-power design of the A/D converter is indispensable to achieve the compact bio-signal measuring device with long battery duration. In this paper, new decimation filter structure is proposed for the low-power design of the Sigma-Delta A/D converter in the bio-instruments. The proposed filter is based on the non-recursive structure of the CIC (Cascaded Integrator Comb) decimation filter in the Sigma-Delta A/D converter. By combining the CSD (Canonic Signed Digit) structure with common sub-expression sharing technique, the proposed decimation filter structure can significantly reduce the number of adders for implementation. For the fixed decimation factor of 16, the 15％ of power consumption saving is achieved in the proposed structure in comparison with that of the conventional polyphase CIC filter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.9
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• pp.31-38
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• 2009

In this paper, we propose new gain optimization method for Sigma-Delta A/D converters. First, in proposed method, the 10 candidates are selected through SNR maximization for Sigma-Delta modulator. After then, it is shown that optimum gains can be obtained through MSE calculation for CIC decimation filter. In the simulation, The proposed method has advantages which utilize SNR maximization for modulator and MSE minimization for CIC decimation later. The more candidates are chosen in SNR maximization for modulator, the better gains can be obtained in MSE minimization for CIC decimation filter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.4
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• pp.1-8
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• 2010

In this paper, we propose a new gain optimization technique for Sigma-Delta A/D converters. In the proposed scheme, multiple gain set candidates showing maximum SNR in the modulator block are selected, and then multiple gain set candidates are investigated for minimum MSE in decimation block. Through CIC decimation filter simulation, it is shown that second SNR ranking candidate in modulation block is the best gain set.

• Journal of IKEEE
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• v.23 no.2
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• pp.461-468
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• 2019

A continuous-time Delta-Sigma ADC has various benefits; it does not require an explicit anti-aliasing filter, and it is able to handle wider-band signals with less power consumption in comparison with a discrete-time Delta-Sigma ADC. However, it inherently needs to sample the signal with a high-speed clock, necessitating a complex decimation filter that operates at high speed in order to convert the modulator output to a low-rate high-resolution digital signals without causing aliasing. This paper proposes a continuous-time Delta-Sigma ADC architecture that employs pulse-width modulation and shows that the proposed architecture lends itself to a simpler implementation of the decimation filter using a lookup table.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.630-638
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• 2001

This paper has been proposed a structure composed of FIRs and IIR filters as digital decimation filter to compensate the drooping inband on the high precision AU chips. The area of chip has been reduced compared with the conventional structure because the RAM and MAC is reduced. The passband ripple$(\leq\; 0.4535 \times fs)$, passband attenuation(at $\; 0.4535 \times fs$ and stopband attenuation$(\geq\; 0.59\times fs)$ of the 6th-order $\Delta\Sigma$ modulator and digital decimation filter had $\pm0.0007[dB]$, -0.0013[dB] and -110[dB] respectively. Also the inband group delay, which was almost same compared with the conventional digital decimation filter structure, was 30.07/fs[s] band the error of group delay was 0.1672%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.2
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• pp.309-314
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• 2008

Analog-to-digital converters(ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental(integrating) data converters(IDCs) provide a solution for such measurement applications, as they retain most of the advantages of conventional $\Delta{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth AC signals over multi-channel is discussed. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.