• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.647-654
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• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2305-2309
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• 2010

In this paper, the variations of threshold voltage characteristics for ratio of channel length and thickness have been alanyzed for DG(Double Gate)MOSFET having top gate and bottom gate. Since the DGMOSFET has two gates, it has advantages that contollability of gate for current is nearly twice and SCE(Short Channel Effects) shrinks in nano devices. The channel length and thickness in MOSFET determines device size and extensively influences on SCEs. The threshold voltage roll-off, one of the SCEs, is large with decreasing channel length. The threshold voltage roll-off and drain induced barrier lowing have been analyzed with various ratio of channel length and thickness for DGMOSFET in this study.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.765-767
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• 2010

In this paper, the variations of threshold voltage characteristics for ratio of channel length and thickness have been alanyzed for DG(Double Gate)MOSFET having top gate and bottom gate. Since the DGMOSFET has two gates, it has advantages that contollability of gate for current is nearly twice and SCE(Short Channel Effects) shrinks in nano devices. The channel length and thickness in MOSFET determines device size and extensively influences on SCEs. The threshold voltage roll-off, one of the SCEs, is large with decreasing channel length. The threshold voltage roll-off has been analyzed with various ratio of channel length and thickness for DGMOSFET in this study.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.170-177
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• 2008

In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1764-1770
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• 2011

In this paper, the subthreshold swings for doping distribution in the channel have been analyzed in double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studying since it can lessen the short channel effects(SCEs) as next -generation nano device. The degradation of subthreshold swing(SS) known as SCEs has greatly influenced on application of digital devices, and has been analyzed for structural parameter and variation of channel doping profile in DGMOSFET. The analytical model of Poisson equation has been derived from nonuniform doping distribution for DGMOSFET. To verify potential and subthreshold swing model based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and subthreshold swing for DGMOSFET has been analyzed using these models.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.92-97
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• 2008

In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1537-1542
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• 2011

In this paper, the subthreshold characteristics have been analyzed for various oxide thickness of double gate MOSFET(DGMOSFET) using Poisson's equation with nonuniform doping distribution. The DGMOSFET is extensively been studying since it can shrink the short channel effects(SCEs) in nano device. The degradation of subthreshold swing(SS) known as SCEs has been presented using analytical for, of Poisson's equation with nonuniform doping distribution for DGMOSFET. The SS have been analyzed for, change of gate oxide thickness to be the most important structural parameters of DGMOSFET. To verify this potential and transport models of thus analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and subthreshold swing has been analyzed using this models for DGMOSFET.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.508-517
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• 2014

We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width ($W_{fin}$) and height ($H_{fin}$) of the fin as well as the channel doping concentration ($N_{ch}$). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.

• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.