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http://dx.doi.org/10.5573/JSTS.2014.14.5.508

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors  

Kim, Sung Yoon (School of Electronics Engineering, Kyungpook National University)
Seo, Jae Hwa (School of Electronics Engineering, Kyungpook National University)
Yoon, Young Jun (School of Electronics Engineering, Kyungpook National University)
Yoo, Gwan Min (School of Electronics Engineering, Kyungpook National University)
Kim, Young Jae (School of Electronics Engineering, Kyungpook National University)
Eun, Hye Rim (School of Electronics Engineering, Kyungpook National University)
Kang, Hye Su (School of Electronics Engineering, Kyungpook National University)
Kim, Jungjoon (School of Electronics Engineering, Kyungpook National University)
Cho, Seongjae (Department of Electronic Engineering, Gachon University,)
Lee, Jung-Hee (School of Electronics Engineering, Kyungpook National University)
Kang, In Man (School of Electronics Engineering, Kyungpook National University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.14, no.5, 2014 , pp. 508-517 More about this Journal
Abstract
We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width ($W_{fin}$) and height ($H_{fin}$) of the fin as well as the channel doping concentration ($N_{ch}$). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.
Keywords
Junctionless; fin-shaped field-effect transistor (FinFET); short-channel effect (SCE); 3-D device simulation;
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Times Cited By KSCI : 5  (Citation Analysis)
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1 P. K Sahu, S. K. Mohapatra, and K. P. Pradhan, "A Study of SCEs and Analog FOMs in GS-DGMOSFET with Lateral Asymmetric Channel Doping," J. Semicond. Technol. Sci., vol. 13, no. 6, pp. 647-654, Dec. 2013.   DOI
2 T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, and F. Boeuf, "The end of CMOS scaling: Toward the introduction of new materials and structural changes to improve MOSFET performance," IEEE Circuits Devices Mag., vol. 21, no. 1, pp. 16-26, Jan. 2005.   DOI
3 C. Hu, "Device challenges and opportunities," in Proc. VLSI Symp. Technol., Jun. 2004, pp. 4-5.
4 S. Borkar, "Circuit techniques for subthreshold leakage avoidance, control, and tolerance," in IEDM Tech. Dig., pp. 421-424, Dec. 2004.
5 S. Gundapaneni, S. Ganguly, and A. Kottantharayil, "Bulk planar junctionless transistor (BPJLT): An attractive device alternative for scaling," IEEE Electron Device Lett., vol. 32, no. 3, pp. 261-263, Mar. 2011.   DOI
6 J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions," Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010.   DOI   ScienceOn
7 N. D. Akhavan, I. Ferain, P. Razavi, R. Yu, and J.-P. Colinge, "Improvement of carrier ballisticity in junctionless nanowire transistors," Appl. Phys. Lett., vol. 98, no. 10, pp. 103510-1-103510-3, Mar. 2011.   DOI
8 R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-orabi, and K. Kuhn, "Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm," IEEE Electron Device Lett., vol. 32, no. 9, pp. 1170-1172, Sep. 2011.   DOI
9 J. S. Lee, S. Cho, B.-G. Park, J. S. Harris, Jr, and I. M. Kang, "Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications," J. Semicond. Technol. Sci., vol. 12, no. 2, pp. 230-239, Jun. 2012.   DOI
10 C.-H. Park, M.-D. Ko, K.-H. Kim, R.-H. Baek, C.-W. Sohn, C. K. Baek, S. Park, M. J. Deen, Y.-H. Jeong, and J.-S. Lee, "Electrical characteristics of 20-nm junctionless Si nanowire transistors," Solid-State Electron., vol. 73, no. 3, pp. 7-10, Jul. 2012.   DOI
11 D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET-A selfaligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.   DOI   ScienceOn
12 Y. Omura, H. Konishi, and K. Yoshimoto, "Impact of Fin Aspect Ratio on Short-Channel Control and Drivability of Multiple-Gate SOI MOSFET's," J. Semicond. Technol. Sci., vol. 8, no. 4, pp. 302-310, Dec. 2008.   DOI
13 SILVACO International, ATLAS User's Manual, Apr. 2012.
14 I. J. Park, and C. Shin, "Monte Carlo Simulation Study: the effects of double-patterning versus single-patterning on the line-edge-roughness (LER) in FDSOI Tri-gate MOSFETs," J. Semicond. Technol. Sci., vol. 13, no. 5, pp. 511-515, Oct. 2013.   DOI
15 F. Najam, S. Kim, and Y. S. Yu, "Gate All Around Metal Oxide Field Transistor: Surface Potential Calculation Method including Doping and Interface Trap Charge and the Effect of Interface Trap Charge on Subthreshold Slope," J. Semicond. Technol. Sci., vol. 13, no. 5, pp. 530-537, Oct. 2013.   DOI
16 B. Lakshmi and R. Srinivasan, "Effect of gate electrode work function in conventional and junctionless FinFETs," Int. J. Phys. Sci., vol. 7, no. 49, pp. 6246-6254, Dec. 2012.
17 A. Nandi, A. K. Saxena, and S. Dasgupta, "Design and Analysis of Analog Performance of Dual-k Spacer Underlap N/P-FinFET at 12 nm Gate Length," IEEE Trans. Electron Devices, vol. 60, no. 5, pp. 1529-1535, May. 2013.   DOI
18 C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J.-P. Colinge, "Performance estimation of junctionless multigate transistors," Solid-State Electron., vol. 54, no. 2, pp. 97-103, Feb. 2010.   DOI   ScienceOn
19 Process Integration, Devices, and Structures (PIDS) Chapter, International Technology Roadmap for Semiconductors (ITRS), 2012 edition.
20 M. Schlosser, K. K. Bhuwalka, M. Sauter, T. Zilbauer, T. Sulima, and I. Eisele, "Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High-${\kappa}$ Gate Dielectrics," IEEE Trans. Electron Devices, vol. 56, no. 1, pp. 100-108, Jan. 2009.   DOI
21 S. Cho, K. R. Kim, B.-G. Park, and I. M. Kang, "RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs," IEEE Trans. Electron Devices, vol. 58, no. 5, pp. 1388-1396, May. 2011.   DOI
22 Y. Tsividis, Operation and Modeling of the MOS Transistor, Oxford University Press, New York, USA, 1999, pp. 467-491, 500-504.