• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.291.2-291.2
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• 2016

3D semiconductor material of silicon that is used throughout the semiconductor industry currently faces a physical limitation of the development of semiconductor process technology. The research into the next generation of nano-semiconductor materials such as semiconductor properties superior to replace silicon in order to overcome the physical limitations, such as the 2-dimensional graphene material in 2D transition-metal dichalcogenide (TMD) has been researched. In particular, 2D TMD doping without severely damage of crystal structure is required different conventional methods such as ion implantation in 3D semiconductor device. Here, we study a p-type doping technique on tungsten diselenide (WSe2) for p-channel 2D transistors by adjusting the concentration of hydrochloric acid through Raman spectroscopy and electrical/optical measurements. Where the performance parameters of WSe2 - based electronic device can be properly designed or optimized. (on currents increasing and threshold voltage positive shift.) We expect that our p-doping method will make it possible to successfully integrate future layered semiconductor devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.66-77
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• 2010

Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.287-298
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• 2007

A two-dimensional treatment of the potential distribution under the depletion approximation is presented for poly-crystalline silicon thin film transistors. Green's function approach is adopted to solve the two-dimensional Poisson's equation. The solution for the potential distribution is derived using Neumann's boundary condition at the silicon-silicon di-oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain-boundaries. Also short-channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.

• 반도체디스플레이기술학회지
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• 제14권4호
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• pp.13-19
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• 2015

In this paper, the principle of devices which can magnify images without distorting the images is described. When the device is put on a smart phones, viewers can see the magnified images. Magnified images can be few 100 times bigger than the original images. Therefore, viewers can see movie theater size images with the device put on a smart phone. Two different schemes are explained in the paper and one realization of the device is presented. The device can be used in many different application areas.

• 반도체디스플레이기술학회지
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• 제14권1호
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• pp.45-49
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• 2015

Process gases with vapor or liquid phase as well as gas phase may experience alteration in itself or be contaminated in the fluid pipe to the process chamber. And thus it result in as particles or defects on the substrates in semiconductor, LCD, LED manufacturing. Purifiers and filters are used for control of contamination. However, none of detection device is available in the delivery line. In this paper, we propose simple device with lighting and sensing in order to predict contamination of the fluid or the tube wall. For some general purpose gases, it showed constant voltage output regardless of the flow rates. But, the smoke and the moisture in the air lowered the figure due to its concentration. Numerical values for several solid and liquid media were obtained. And, the operating temperature tendency was investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.370-376
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• 2012

In this work, design considerations for high-performance silicon photodetector are thoroughly investi- gated. Besides the critical dimensions of device, guidelines for process architecture are suggested. Abiding by those criteria for improving both direct-current (DC) and alternating-current (AC) perfor- mances, a high-speed low-operation power silicon photodetector based on p-i-n structure for optical interconnect has been designed by device simulation. An $f_{-3dB}$ of 80 GHz at an operating voltage of 1 V was obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.1023-1026
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• 2007

Highly efficient inverted bottom emission organic light emitting device (IBOLED) with a structure of ITO/EIL/Alq3/NPB/WO3/Al was investigated. To enhance electron injection from ITO cathode to Alq3 EML layer, we introduced ultra thin Al layer and Liq layer between ITO and Alq3. The device characteristics showed tune on voltage of 4.5V, the maximum luminance of 21100 Cd/m2 and current efficiencies of 3.56 Cd/A.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.174-179
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• 2017

We designed the CMOS analog integrate and fire (I&F) neuron circuit for driving memristor based on resistive-switching random access memory (RRAM). And we fabricated the RRAM device that have $HfO_2$ switching layer using atomic layer deposition (ALD). The RRAM device has gradual set and reset characteristics. By spice modeling of the synaptic device, we performed circuit simulation of synaptic device and CMOS neuron circuit. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, two inverters for pulse generation, a refractory part, and finally a feedback part for learning of the RRAM. We emulated the spike-timing-dependent-plasticity (STDP) characteristic that is performed automatically by pre-synaptic pulse and feedback signal of the neuron circuit. By STDP characteristics, the synaptic weight, conductance of the RRAM, is changed without additional control circuit.

• 반도체디스플레이기술학회지
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• 제21권2호
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• pp.15-18
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• 2022

The ultraviolet-C emitting praseodymium doped yttrium phosphate (YPO₄:Pr³⁺) powder was synthesized by conventional solid-state reaction. The electroluminescence device was fabricated by simple screen-printing method using the synthesized YPO₄:Pr³⁺ powder, especially, polyvinylidene fluoride as an insulating layer was applied on the printed YPO₄:Pr³⁺ powder for stable performance of the electroluminescence. The electroluminescence properties were investigated under alternating current power system of 400 Hz. The device starts to emit at 350 V, which showed the ultraviolet-C emission peaking at the 233, 245, 264, 273 nm attributed to electronic transition of the Pr³⁺ ions. The electroluminescence intensity was increased as increasing the operating voltage and the device revealed stable performance up to 600 V due to the polyvinylidene fluoride serve as a protective layer.

• 한국안전학회지
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• 제15권4호
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• pp.62-68
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• 2000

Static electricity in electronics manufacturing plants causes the economic loss, yet it is one of the least understood and least recognized effects haunting the industry today. Today's challenge in semiconductor devices is to achieve greater functional density pattern and to miniaturize electronic systems of being more fragile by electrostatic discharges(ESD) phenomena. As the use of automatic handling equipment for static-sensitive semiconductor components is rapidly increased, most manufacturers need to be more alert to the problem of ESD. One of the most common causes of electrostatic damage is the direct transfer of electrostatic charge from the human body or a charged material to the static-sensitive devices. To evaluate the ESD hazards by charged human body and devices, in this paper, characteristics of electrostatic attenuation in domestic semiconductor devices is investigated and the voltage to cause electronic component failures is investigated by field-induced charged device model(FCDM) tester. The FCDM simulator provides a fast and inexpensive test that faithfully represents ESD hazards in plants. Also the results obtained in this paper can be used for the prevention of semiconductor failure from ESD hazards.