• Proceedings of the Optical Society of Korea Conference
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• 1991.06a
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

• Journal of the Korean Magnetics Society
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• v.15 no.6
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• pp.332-335
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• 2005

Output voltage of the flux-meter has always drift due to the input bias current of non-ideal operational amplifier. In this study we have employed a digital sample and hold amplifier which has no voltage drop to compensate drift of the flux-meter automatically. The drift of the developed flux-meter was smaller than $5{\times}10^{-8}\;Wb/s$ for the integration time constant of $RC=10^{-3}$ s.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.390.1-390.1
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• 2016

The present work explains the interfacial energetics of all oxide transparent photodiodes. The optical, structural and morphological of copper oxides were systematically analyse by UV-Visible spectrometer, X-Ray diffraction, Raman spectroscopy, Scanning electron microscopy (SEM) and Atomic force microscopy measurements (AFM). The UV-Visible result exhibits optical bandgap of Cu2O and CuO as 2.2 and 2.05 eV respectively. SEM and AFM result shows a uniform grain size distribution in Cu2O and CuO thin films with the average grain size of 45 and 40 nm respectively. The results of Current-Voltage and Kelvin probe force microscope characteristics describe the electrical responses of the Cu2O/ZnO and CuO/ZnO heterojunctions photodiodes. The obtained electrical response depicts the approximately same knee voltages with a measurable difference in the absolute value of net terminal current. More over the present study realizes the all oxide transparent photodiode with zero bias photocurrent. The presented results lay the template for fabricating and analysing the self-bias all oxide transparent photodetector.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.678-681
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• 2009

A single-pixel photon counter is designed using a folded cascode CMOS operational amplifier which is self-biased. Since there is no need for a voltage bias circuit, the layout area and power consumption of the designed counter are reduced. The signal voltage of the designed charge sensitive amplifier (CSA) with the MagnaChip $0.18{\mu}m$ CMOS process is simulated to be 138mv, near the theoretical voltage of 151mV. And the layout area of the designed counter is $100{\mu}m{\times}100{\mu}m$.

• Electrical & Electronic Materials
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• v.10 no.10
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• pp.1000-1004
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• 1997

In this paper the current-voltage characteristics of a submicron GaAs MESFET is simulated by using the self-consistent ensemble Monte Carlo method. The numerical algorithm employed in solving the two-dimensional Poisson equation is the successive over-relaxation(SOR) method. The total number of employed superparticles is about 1000 and the field adjusting time is 10fs. To obtain the steady-state results the simulation is performed for 10ps at each bias condition. The simulation results show the average electron velocity is modified by the gate voltage.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1877-1880
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• 2005

This paper proposed the new current feed-back amplifier for low supply voltage application. The input stage was designed to be a class-AB circuit and achieve the low supply-voltage operation down to $2V_{TH}+2V_{DS(SAT)}$. With the self-adjust bias current, the high performance can be adopted with high stability. The circuit was successfully proven by the simulation with MOSIS 0.5 ${\mu}$m MOS technology.

• ETRI Journal
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• v.32 no.1
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• pp.68-72
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• 2010

The coupling between the transverse and longitudinal components of the channel electron motion in NMOS devices leads to a reduction in the barrier height. Therefore, this study theoretically investigates the effects of the in-plane velocity of channel electrons on the capacitance-voltage characteristics of nano NMOS devices under inversion bias. Numerical calculation via a self-consistent solution to the coupled Schrodinger equation and Poisson equation is used in the investigation. The results demonstrate that such a coupling largely affects capacitance-voltage characteristic when the in-plane velocity of channel electrons is high. The ballistic transport ensures a high in-plane momentum. It suggests that such a coupling should be considered in the quantum capacitance-voltage modeling in ballistic transport devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.526-532
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• 2015

We quantitatively investigated instability mechanisms under simultaneous positive gate and drain bias stress (SPGDBS) in self-aligned top-gate amorphous indium-zinc-oxide thin-film transistors. After SPGDBS ($V_{GS}=13V$and $V_{DS}=13V$), the parallel shift of the transfer curve into a negative $V_{GS}$ direction and the increase of on current were observed. In order to quantitatively analyze mechanisms of the SPGDBS-induced negative shift of threshold voltage (${\Delta}V_T$), we experimentally extracted the density-of-state, and then analyzed by comparing and combining measurement data and TCAD simulation. As results, 19% and 81% of ${\Delta}V_T$ were taken to the donor-state creation and the hole trapping, respectively. This donor-state seems to be doubly ionized oxygen vacancy ($V{_O}^{2+}$). In addition, it was also confirmed that the wider channel width corresponds with more negative ${\Delta}V_T$. It means that both the donor-state creation and hole trapping can be enhanced due to the increase in self-heating as the width becomes wider. Lastly, all analyzed results were verified by reproducing transfer curves through TCAD simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.1-7
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• 2006

An on chip voltage down converter (VDC) using the self temperature-compensation techniques is proposed. At a different gate bias voltage, PMOSFET shows different source to drain current characteristic according to the temperature variation. The proposed VDC can reduce its temperature dependency by the source to drain current ratio of two PMOSFET with different gate bias respectively. Proposed circuit is fabricated in Dongbu-anam $0.18{\mu}m$ CMOS process and experimental results show its temperature dependency of $-0.49mV/^{\circ}C$ and external supply dependency of 6mV/V. Total current consumption is only $1.1{\mu}A@2.5V$.

• Bulletin of the Korean Chemical Society
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• v.29 no.2
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• pp.438-444
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• 2008

A self-assembled monolayer of 2,2'-bipyridine (22BPY) molecules on Au(111) underwent a structural phase transition when the polarity of a bias voltage was switched in scanning tunneling microscopy (STM) experiments. The nature of two bright spots representing each 22BPY molecule on Au(111) in the high-resolution STM images was identified by calculating the partial density plots for a monolayer of 22BPY molecules adsorbed on Au(111) using tight-binding electronic structure calculations. The stacking pattern of the chains of 22BPY molecules on Au(111) was explained by examining the intermolecular interactions between the 22BPY molecules based on first principles electronic structure calculations for a 22BPY dimer, (22BPY)2. The structural instability of the 22BPY molecule arrangement caused by a change in the bias voltage switch was investigated by estimating the adsorbate-surface interaction energy using a point-charge approximation for Au(111).