• Wind and Structures
• /
• v.32 no.3
• /
• pp.227-238
• /
• 2021

This study analyzed the pressure patterns and local pressure of tall buildings with corner modifications (recessed and chamfered corner) using wind tunnel tests and proper orthogonal decomposition (POD). POD can distinguish pressure patterns by POD mode and more dominant pressure patterns can be found according to the order of POD modes. Results show that both recessed and chamfered corners effectively reduced wind-induced responses. Additionally, unique effects were observed depending on the ratio of corner modification. Tall building models with recessed corners showed fluctuations in the approaching wind flow in the first POD mode and vortex shedding effects in the second POD mode. With large corner modification, energy distribution became small in the first POD mode, which shows that the effect of the first POD mode reduced. Among building models with chamfered corners, vortex shedding effects appeared in the first POD mode, except for the model with the highest ratio of corner modifications. The POD confirmed that both recessed and chamfered corners play a role in reducing vortex shedding effects, and the normalized power spectral density peak value of modes showing vortex shedding was smaller than that of the building model with a square section. Vortex shedding effects were observed on the front corner surfaces resulting from corner modification, as with the side surface. For buildings with recessed corners, the local pressure on corner surfaces was larger than that of side surfaces. Moreover, the average wind pressure was effectively reduced to 88.42% and 92.40% in RE1 on the windward surface and CH1 on the side surface, respectively.

• Korean Journal of Materials Research
• /
• v.13 no.1
• /
• pp.11-17
• /
• 2003

DC characteristics of recessed gate 4H-SiC MESFET were investigated using the device/circuit simulation tool, PISCES. Results of theoretical calculation were compared with the experimental data for the extraction of modeling parameters which were implemented for the prediction of DC and gate leakage characteristics at high temperatures. The current-voltage analysis using a fixed mobility model revealed that the short channel effect is influenced by the defects in SiC. The incomplete ionization models are found out significant physical models for an accurate prediction of SiC device performance. Gate leakage is shown to increase with the device operation temperatures and to decrease with the Schottky barrier height of gate metal.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.635-640
• /
• 2016

Tunnel field-effect transistor (TFET) is a promising candidate for the next-generation electron device. However, technical issues remain for their practical application: poor current drivability, shor-tchannel effect and ambipolar behavior. We propose herein a novel recessed-channel TFET (RTFET) with the asymmetric source and drain. The specific design parameters are determined by technology computer-aided design (TCAD) simulation for high on-current and low S. The designed RTFET provides ${\sim}446{\times}$ higher on-current than a conventional planar TFET. And, its average value of the S is 63 mV/dec.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.4
• /
• pp.106-110
• /
• 1997

A new SOI NMOSFET with a 'LOCOS-like' shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication was tried. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3${\mu}{\textrm}{m}$ SOI devices with V\ulcorner of 0.77V and Tox=7.6nm is 360$mutextrm{A}$/${\mu}{\textrm}{m}$ at V\ulcorner\ulcorner=3.5V and V\ulcorner=2.5V. Improved breakdown characteristics were obtained and the BV\ulcorner\ulcorner\ulcorner(the drain voltage for 1 nA/${\mu}{\textrm}{m}$ of I\ulcorner at V=\ulcorner\ulcorner=0V) of the device with L\ulcorner\ulcorner=0.3${\mu}{\textrm}{m}$ under the floating body condition was as high as 3.7 V. Problems for the new scheme are also addressed and more advanced device structure based on the proposed scheme is proposed to solve the problems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.497-500
• /
• 1999

This paper reports on the fabrication and characteristics of recessed gate GaN MESFETs fabricated using a photoelectrochemical wet etching method. The unique etching process utilizes photo-resistive mask and KOH based etchant. GaN MESFETs with successfully recessed gate structure was characterized in terms of dc and RF performance. The fabricated GaN MESFET exhibits a current saturation at $V_{DS}$ = 4 V and a pinch-off at $V_{GS}$ =-3V The peak drain current of the device is about 230mA/mm at 300 K and the value is remained almost same for 500K operation. The $f_{T}$ and $f_{max}$ from the device are 6.357Hz and 10.25 GHz, respectively.y.y.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.1
• /
• pp.61-65
• /
• 2010

Threshold voltage is one of the most important factors in a device modeling. In this paper, analytical method to calculate threshold voltage for recessed channel (RC) MOSFETs is studied. If we know the fundamental parameter of device, such as radius, oxide thickness and doping concentration, threshold voltage can be obtained easily by using this model. The model predicts the threshold voltage which is the result of 2D numerical device simulation.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.12
• /
• pp.159-165
• /
• 1995

A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage is observed compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.5
• /
• pp.497-503
• /
• 2015

It is essential to acquire an accurate and simple technique for extracting the interface trap density ($D_{it}$) in order to characterize the normally-off gate-recessed AlGaN/GaN hetero field-effect transistors (HFETs) because they can undergo interface trap generation induced by the etch damage in each interfacial layer provoking the degradation of device performance as well as serious instability. Here, the frequency-dependent capacitance-voltage (C-V) method (FDCM) is proposed as a simple and fast technique for extracting $D_{it}$ and demonstrated in normally-off gate-recessed AlGaN/GaN HFETs. The FDCM is found to be not only simpler than the conductance method along with the same precision, but also much useful for a simple C-V model for AlGaN/GaN HFETs because it identifies frequency-independent and bias-dependent capacitance components.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.366-367
• /
• 2006

In general, HF chemistry lifts off the particles during scrubbing after polishing and effectively removes particles. It is sometimes impossible to apply HF chemistry on W plug due to the degradation of electrical characteristics of a device. In this paper, a post W CMP cleaning process is proposed to remove residue particles without applying HF chemistry. After W CMP, recessed plugs are created, therefore they easily trap slurry particles during CMP process. These particles in recessed plug are not easy to remove by brush scrubbing when $NH_4OH$ chemistry is used for the cleaning because the brush surface can not reach the recessed area of plugs. Buffing with oxide slurry was followed by W CMP due to its high selectivity to W. The buffing polishes only oxide slightly which creates higher plug profiles than surrounding oxide. Higher profiles make the brush contact much more effectively and result in a similar particle removal efficiency even in $NH_4OH$ cleaning to that in HF brush scrubbing.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.08a
• /
• pp.264-264
• /
• 2011

1T-1C로 구성되는 기존의 dynamic random access memory (DRAM)는 데이터를 저장하기 위해 적절한 커패시턴스를 확보해야 한다. 따라서 커패시터 면적으로 인한 집적도의 한계에 직면해있으며, 이를 대체하기 위한 새로운 DRAM인 1T- DRAM이 연구되고 있다. 기존의 DRAM과 달리 silicon-on-insulator (SOI) 기술을 이용한 1T-DRAM은 데이터 저장을 위한 커패시터가 요구되지 않는다. 정공을 채널의 중성영역에 축적함으로서 발생하는 포텐셜 변화를 이용하며, 이때 발생하는 드레인 전류차를 이용하여 '0'과 '1'을 구분한다. 기존의 완전공핍형 평면구조의 1T-DRAM은 소스 및 드레인 접합부분에서 발생하는 누설전류로 인해 '0' 상태의 메모리 유지특성이 열화되는 단점을 가지고 있다. 따라서 메모리의 보존특성을 향상시키기 위해 소스/드레인 접합영역을 줄여 누설전류를 감소시키는 구조를 갖는 1T-DRAM의 연구가 필요하다. 또한 고유전율을 가지는 Si3N4를 이용한 oxide-nitride-oxide (ONO)구조의 게이트 절연막을 이용하면 동일한 두께에서 더 낮은 equivalent oxide thickness (EOT)를 얻을 수 있기 때문에 보다 저 전압에서 1T-DRAM 동작이 가능하여 기존의 SiO2 단일층을 이용한 1T-DRAM보다 동일 전압에서 더 큰 sensing margin을 확보할 수 있다. 본 연구에서는 누설전류를 감소시키기 위하여 소스 및 드레인이 채널위로 올려진 recessed channel 구조에 ONO 게이트 절연막을 적용한 1T-DRAM을 제작 및 평가하고, 본 구조의 1T-DRAM적용 가능성 및 ONO구조의 게이트 절연막을 이용한 sensing margin 개선을 확인하였다.