Analytic Threshold Voltage Model of Recessed Channel MOSFETs |
Kwon, Yong-Min
(Inter-University Semiconductor Research Center (ISRC), and School of Electrical Engineering, Seoul National University)
Kang, Yeon-Sung (Inter-University Semiconductor Research Center (ISRC), and School of Electrical Engineering, Seoul National University) Lee, Sang-Hoon (Inter-University Semiconductor Research Center (ISRC), and School of Electrical Engineering, Seoul National University) Park, Byung-Gook (Inter-University Semiconductor Research Center (ISRC), and School of Electrical Engineering, Seoul National University) Shin, Hyung-Cheol (Inter-University Semiconductor Research Center (ISRC), and School of Electrical Engineering, Seoul National University) |
1 | S.H. Goodwin and J.D. Plummer, “Electrical performance and physics of isolation region structure for VLSI,” IEEE Trans. Elctron Devices, Vol. ED-31, No.7, pp.861-872, 1984. DOI ScienceOn |
2 | K. Natori, I. Sasaki, and F. Masuoka, “An analysis of the concave MOSFET,” IEEE Trans. Elctron Devices, Vol.ED-25, No.4, pp.448-456, 1978. DOI ScienceOn |
3 | P. Bricout and E. Dubois, “Short-channel effect immunity and current capability of sub-0.1 micron MOSFETs using recessed channel,” IEEE Trans. Elctron Devices, Vol.43, No.8, pp.1251-1255, 1996. DOI ScienceOn |
4 | S. G. Chamberlain and S. Ramanan, “Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations,” IEEE Trans. Elctron Devices, Vol.ED-33, No.11, pp.1745-1753, 1986 DOI ScienceOn |
5 | J. Lee, “ Two-Bit/Cell NFGM Devices for High-Density NOR Flash Memory, ” Journal of Semiconductor Technology and Science, Vol.8, No.1, pp.11-20, 2008 과학기술학회마을 DOI ScienceOn |
6 | Atlas Device Simulation Software, Ver. 5.10.7.R, Silvaco International, Santa Clara, CA, 2006. |