• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• ETRI Journal
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• v.42 no.5
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• pp.790-798
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• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.

• The Journal of the Acoustical Society of Korea
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• v.14 no.5
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• pp.29-35
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• 1995

Nonlinear distortion arising from the nonlinear movement of the loudspeaker diaphragm degradates the tone quality. The distortion is, in low frequency range, mainly caused by nonlinear characteristics of the suspension stiffness and the force factor. In this paper, the nonlinear suspension stiffness and the nonlinear force factor are modeled to the quadratic functions and a method is proposed to determine their coefficients. An additional mass to the diaphragm moved the quiescent point of the diaphragm and uncoupled the stiffness and the force factor. This made it possible to deter mine the coefficients of the nonlinear suspension stiffness by measuring the resonance frequencies at several quiescent points. The coefficients of the nonlinear force factor are then determined by fitting the curve which is calculated from the waveforms of input voltage and input current, and the displacement of the diaphragm at resonance frequency.

• Journal of the Korean institute of surface engineering
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• v.27 no.3
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• pp.158-165
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• 1994

Cu-Cr alloy thin film requires good quality of etching be used for TAB technology. The etched cross sec-tion was clean enough when the etching was performed in 0.1M $FeCl_3$ solution at $50^{\circ}C$. The etching rate was increased with the amount of $KMnO_4$. For enhanced profile of cross section and rate, the spray etchning was found to be superior compared to the immersion etching. A series of experiments were performed to improve the uniformity of the current distribution in electrodeposition onto the substrate with lithographic patterns. Copper was electrodeposited from quiescent-solution, paddle-agitated-solution, and air-bubbled-solution to in-vestigate the effect of the fluid flow. The thickness profile of the specimen measured by profilmetry has the non uniformity at feature scale in quiescent-solution, because of the longitudinal vortex roll caused by the natural convection. However, uniform thickness profile was achieved in paddle-agitated or air bubbled solu-tion.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.263-271
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• 2013

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in $0.18-{\mu}m$ high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for $1{\mu}F$ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV, $7.5{\mu}A$, and higher than 1 MHz, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.974-984
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• 2000

A CMOS voltage driver circuit for voltage down converter is proposed. An adaptive biasing technique is used to enhance load regulation characteristics. The proposed driver circuit uses the NMOS transistor as a driving transistor, so it does not suffer from large Miller capacitances which is one of the problems with conventional PMOS driving transistor, and hence achieves good phase margin and stable frequency response. No additional complex circuit for frequency compensation such as compensation capacitor is required in this implementation. For the same current capability, the size of NMOS transistor in driver circuit is smaller than that of PMOS counterpart. So the smaller die area can be achieved. The circuits is implemented using a 0.8 ${\mu}{\textrm}{m}$ CMOS process and has a die area of 150 ${\mu}{\textrm}{m}$ x 360 ${\mu}{\textrm}{m}$. Proposed circuit has a quiescent power of 60 . In the current driving range from 100 $mutextrm{A}$ to 50 ㎃, load regulation of 5.6 ㎷ is measured.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.96-102
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• 2002

Current testing(Iddq testing) on monitoring the quiescent power supply current is an efficient and effective method for CMOS bridging faults. The applicability of this technique, however, requires careful examination. Since cardinality of bridging fault is O($n^2$) and current testing requires much longer testing time than voltage testing, it is important to note that a bridging fault is untestable if the two bridged nodes have the same logic values at all times. Such faults should be identified by a good ATPG tool; otherwise, the fault coverage can become skewed. In this paper, we present an object-oriented redundant fault detection scheme for efficient current testing. Experimental results for ISCAS benchmark circuits show that the improved method is more effective than the previous ones.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.313-319
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• 2012

The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-${\mu}m$ standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38-dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-${\mu}A$.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.686-689
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• 2003

This paper describes two kind of new concept for low power consumption for small area TFT-LCDs. First, the proposed analog buffer could reduce the static current by adopting new scheme. Second, new data driver structure reduced DC power consumption by reducing the number of operational amplifier (op-amp). As simulation results of Hspice, the quiescent current of proposed analog buffer is less than $0.8{\mu}A$ and the DC power consumption is reduced about $40{\sim}50%$ compared with conventional ones.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.