• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1693-1698
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• 2015

This paper proposed a PFM(pulse-frequency modulator) boost converter which has dual pulse-width. The PFM boost converter is composed of BGR(band gap voltage reference generating circuit), voltage reference generating circuit, soft-start circuit, error amplifier, high-speed comparator, inductor current sensing circuit and pulse-width generator. Converter has different inductor peak current so it has wider load current range and smaller output voltage ripple. Proposed PFM boost converter generates 18V output voltage with input voltage of 3.7V and it has load current range of 0.1~300mA. Simulation results show 0.43% output voltage ripple at ligh load mode and 0.79% output voltage ripple at heavy load mode. Converter has efficiency 85% at light lode mode and it has maximum 86.4% at 20mA load current.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1612-1614
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• 1994

Modulators Installed in PLS(Pohang Light Source) Linac are composed of a DC high voltage section, a charging section and a discharging section. PFN is charged by a resonant charging mechanism, and discharged by a switching device through the primary of the pulse transformer connected to a load. Charged PFN voltage must be well regulated to obtain stable output pulse voltage at the load. For this purpose, DCHV is controlled by a SCR controller with feedback signal, and PFN voltage is regulated by a De-Q'ing circuit. The full power operation test shows the pulse voltage regulation within ${\pm}0.13%$ with SCR feedback control alone, and within ${\pm}0.08%$ together with De-Q'ing. This paper describes the design concept and operational characteristics of the De-Q'ing circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.1-9
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• 2008

This paper suggests the triple-mode CMOS DC-DC converter that has temperature/voltage variation compensation techniques. The proposed triple-mode CMOS DC-DC converter is used to generate constant or variable voltages of 0.6-2.2V within battery source range of 3.3-5.5V. Also, it supports triple modes, which include Pulse Width Modulator (PWM) mode, Pulse Frequency Modulator (PFM) mode and Low Drop-Out (LDO) mode. Moreover, it uses 1MHz low-power CMOS ring oscillator that will compensate malfunction of chip in temperature/voltage variation condition. The proposed triple-mode CMOS DC-DC converter, which generates output voltages of 0.6-2.2V with an input voltage sources of 3.3-5.5V, exhibits the maximum output ripple voltage of below 10mV at PWM mode, 15mV at PFM mode and 4mV at LDO mode. And the proposed converter has maximum efficiency of 93% at PWM mode. Even at $-25{\sim}80^{\circ}C$ temperature variations, it has kept the output voltage level within 0.8% at PWM/PFM/LDO modes. For the verification of proposed triple-mode CMOS DC-DC converter, the simulations are carried out with $0.35{\mu}m$ CMOS technology and chip test is carried out.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.10
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• pp.513-519
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• 2001

This paper proposed a random sigma-delta modulator(RSDM), which is constructed by a 1st order sigma-delta modulator(SDM) and a simple structured random binary generator(RBG). The 1st order SDM produces a switching pulse waveform which has the same low-frequency component as the reference input, while the RBG spreads the distribution of the number of sampling per switching cycle, and thus disperses the spectrum spikes in the output. The relationship between the harmonic spectra and the number of sampling per switching cycle is studied through computer simulations, and the frequency spectra of the RSDM are confirmed in an experimental setup.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.41-48
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• 2002

This paper presents a 18-mW, 2.5-㎓ fractional-N frequency synthesizer with l-bit $4^{th}$-order interpolative delta-sigma ($\Delta{\;}$\sum$)modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a $0.5-\mu\textrm{m}$ 15-GHz $f_t$ BiCMOS. Synthesizing 2.1 GHzwith less than 200 Hz resolution, it exhibits an in-band phase noise of less than -85 dBc/Hz at 1 KHz offset frequency with a reference spur of -85 dBc and no fractional spurs. The synthesizer also shows phase noise of -139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.8
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• pp.120-127
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• 1996

Anti-lock Brake System has been developed to reduce tendency for wheel lock and improve vehicle control during sudden braking on slippery road surfaces. This is achieved by controlling the braking pressure, avoiding wheel lock, while retaining handling and brake performance. This paper is concerned about pressurecharacteristics of hydraulic modulator. Experimental sets which is consists of hydraulic modulator, duty controller, pressure regulator, pressure senset is consuructed. System modelling and computer simulation are performed for comparison with experimental results. Brake wheel pressure are measured under various driving pulse. The result of experiment show fairly agreement with the simulation. As a result, it is known that wheel pressure is affected by duty ratio, orifice diameter through computer simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1386-1388
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• 2008

본 논문에서는 820.11n 규격에 적합한 Fractional-N 주파수 합성기를 설계하였다. 본 논문에서 설계한 주파수 합성기의 특징은 PFD(Phase Frequency Detector) 뒷단에 잔여 펄스를 제거하는 Pulse Remover를 연결하여 이중 궤환 Charge Pump의 안정도를 향상시켰으며, Charge Pump에서 동시에 발생하는 Up/Down 전류로 인한 Spike성 전류를 없앰으로서 스퓨리어스를 최소화 시켰다. Pulse Removed PFD를 사용함으로서 발생하는 PFD Deadzon문제는 2N+2분주와 2N-2분주기를 3차의 ${\Delta}{\Sigma}$ Modulator가 선택해줌으로 해결하였다. 삼성 0.18u 공정을 이용하여 설계 하였으며 각 블락은 Cadence spectre 를 이용하여 검증하였다.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.19 no.4
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• pp.37-43
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• 2011

Lunar exploration program has been prepared with the aim of launch in the 2020's. As part of it, a lunar lander demonstrator has been developed which is the model for verifying all the system, such as structure, propulsion and control system before launch to deep space. After verifying all the system, the demonstrator will be evaluated by flight test. This paper deals with path tracking controller based on thrusters for the demonstrator. For this, first we derive equations of motion according to the allocation of thrusters and design the path tracking controller. The signal generated from the controller is continuous so PWPF(Pulse-Width Pulse-Frequency) modulator is adopted for generating on/off signal. Finally MATLAB simulation is performed for evaluating the path tracking ability and the final landing velocity.