A High-Efficiency, Robust Temperature/voltage Variation, Triple-mode DC-DC Converter

고효율, Temperature/voltage 변화에 둔감한 Triple-mode CMOS DC-DC Converter

  • Lim, Ji-Hoon (School of Electronic Engineering Soongsil University) ;
  • Ha, Jong-Chan (School of Electronic Engineering Soongsil University) ;
  • Kim, Sang-Kook (School of Electronic Engineering Soongsil University) ;
  • Wee, Jae-Kyung (School of Electronic Engineering Soongsil University)
  • Published : 2008.06.25

Abstract

This paper suggests the triple-mode CMOS DC-DC converter that has temperature/voltage variation compensation techniques. The proposed triple-mode CMOS DC-DC converter is used to generate constant or variable voltages of 0.6-2.2V within battery source range of 3.3-5.5V. Also, it supports triple modes, which include Pulse Width Modulator (PWM) mode, Pulse Frequency Modulator (PFM) mode and Low Drop-Out (LDO) mode. Moreover, it uses 1MHz low-power CMOS ring oscillator that will compensate malfunction of chip in temperature/voltage variation condition. The proposed triple-mode CMOS DC-DC converter, which generates output voltages of 0.6-2.2V with an input voltage sources of 3.3-5.5V, exhibits the maximum output ripple voltage of below 10mV at PWM mode, 15mV at PFM mode and 4mV at LDO mode. And the proposed converter has maximum efficiency of 93% at PWM mode. Even at $-25{\sim}80^{\circ}C$ temperature variations, it has kept the output voltage level within 0.8% at PWM/PFM/LDO modes. For the verification of proposed triple-mode CMOS DC-DC converter, the simulations are carried out with $0.35{\mu}m$ CMOS technology and chip test is carried out.

본 논문에서는 temperature/voltage에 둔감한 triple-mode CMOS DC-DC Converter를 제안한다. 제안된 triple-mode DC-DC converter는 단일 배터리의 수명에 따른 전압변화(3.3-5.5V)로부터 일정 또는 다양한 출력전압(0.6-2.2V)을 생성한다. 제안된 triple-mode CMOS DC-DC converter는 Pulse Width Modulator(PWM) 모드, Pulse Frequency Modulator(PPM) 모드, 그리고 Low Drop-Out(LDO) 모드, 이렇게 세 가지 모드로 동작한다. 또한, 제안된 회로는 temperature/voltage 변화에 의한 칩의 오동작을 방지하기 위해 temperature/voltage 변화에 둔감한 저 전력 1MHz CMOS ring oscillator를 사용한다. 제안된 triple-mode DC-DC converter는 단일 입력 전원소스(3.3-5.5V)에서 출력 전압(0.6-2.2V)을 생성하며, 출력 전압 ripple은 PWM mode에서 10mv, PFM mode에서 15mV, 그리고 LDO mode에서는 4mV 이하이다. 또한, 제안된 회로의 효율은 PWM mode에서 93% 이상이며, $-25-80^{\circ}C$의 온도변화에도 각 모드에서의 출력 전압 레벨의 오차는 단지 0.8% 이하로 유지한다 제안된 회로의 검증을 위해 CMOS $0.35{\mu}m$ 공정을 이용한 시뮬레이션 및 칩 테스트를 수행하였다.

Keywords

References

  1. Xiao. J, Peterchev. A, Zhang. J, Sanders. S, "An ultra-low-power digitally-controlled buck converter IC for cellular phone", Applied Power Electronics Conference and Exposition, pp383-391, 2004
  2. Sahu. B, Ricon-Mora. G. A, "A high-efficiency, dual-mode, dynamic, buck-boost power supply IC for portable applications", VLSI Design 18th International Conference, pp858-861, Jan 2005
  3. Qiang Biasn, Zushu Yan, Yuanfu Zhao, Suge Yue, "Analysis and design of voltage controlled current source for LDO frequency compensation", Electron Devices and Solid-State Circuits, 2005 IEEE Conference on, pp363-366, Dec. 2005
  4. Ka Nang Leung, Mok. P.K.T, "A capacitor-free CMOS low-dropout regulator with damping- factor-control frequency compensation", IEEE Journal of Solid-State Circuits, pp1691-1702, Oct. 2003
  5. J. H. Lim, J. C. Ha, W. Y. JUNG, Y. J. KIM, J. K. Wee, "A novel high-speed and low-voltage CMOS level-up/down Shifter design for multiple-power and multiple-clock domain", IEICE, Trans. pp644-648, March 2007
  6. Azais. F, Bernard. S, Bertrand. Y, Michel. X, Renovell. M, "A low-cost adaptive ramp generator for analog BIST applications", VLSI Test Symposium, pp266-271, 2001