• Title/Summary/Keyword: process pump

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Enhanced Bioslurping System for Remediation of Petroleum Contaminated Soils (Enhanced Bioslurping system을 이용한 유류오염 토양의 복원)

  • Kim Dae-Eun;Seo Seung-Won;Kim Min-Kyoung;Kong Sung-Ho
    • Journal of Soil and Groundwater Environment
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    • v.10 no.2
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    • pp.35-43
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    • 2005
  • Bioslurping combines the three remedial approaches of bioventing, vacuum-enhanced free-product recovery, and soil vapor extraction. Bioslurping is less effective in tight (low-permeability) soils. The greatest limitation to air permeability is excessive soil moisture. Optimum soil moisture is very soil-specific. Too much moisture can reduce air permeability of the soil and decrease its oxygen transfer capability. Too little moisture will inhibit microbial activity. So Modified Fenton reaction as chemical treatment which can overcome the weakness of Bioslurping was experimented for simultaneous treatment. Although the diesel removal efficiency of SVE process increased in proportion to applied vacuum pressure, SVE process was difficulty to remediation quickly semi- or non-volatile compounds absorbed soil strongly. And SVE process had variation of efficiency with distance from the extraction well and depth a air flow form of hemisphere centering around the well. Below 0.1 % hydrogen peroxide shows the potential of using hydrogen peroxide as oxygen source but the co-oxidation of chemical and biological treatment was impossible because of the low efficiency of Modified Fenton reaction at 0.1 % (wt) hydrogen peroxide. NTA was more efficiency than EDTA as chelating agent and diesel removal efficiency of Modified Fenton reaction increased in proportion to hydrogen peroxide concentration. Hexadecane as typical aliphatic compound was removed less than Toluene as aromatic compound because of its structural stability in Modified Fenton reaction. What minimum 10% hydrogen peroxide concentration has good remediation efficiency of diesel contaminated groundwater may show the potential use of Modified Fenton reaction after bioslurping treatment.

Process Suggestion and HAZOP Analysis for CQ4 and Q2O in Nuclear Fusion Exhaust Gas (핵융합 배가스 중 CQ4와 Q2O 처리공정 제안 및 HAZOP 분석)

  • Jung, Woo-Chan;Jung, Pil-Kap;Kim, Joung-Won;Moon, Hung-Man;Chang, Min-Ho;Yun, Sei-Hun;Woo, In-Sung
    • Korean Chemical Engineering Research
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    • v.56 no.2
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    • pp.169-175
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    • 2018
  • This study deals with a process for the recovery of hydrogen isotopes from methane ($CQ_4$) and water ($Q_2O$) containing tritium in the nuclear fusion exhaust gas (Q is Hydrogen, Deuterium, Tritium). Steam Methane Reforming and Water Gas Shift reactions are used to convert $CQ_4$ and $Q_2O$ to $Q_2$ and the produced $Q_2$ is recovered by the subsequent Pd membrane. In this study, one circulation loop consisting of catalytic reactor, Pd membrane, and circulation pump was applied to recover H components from $CH_4$ and $H_2O$, one of $CQ_4$ and $Q_2O$. The conversion of $CH_4$ and $H_2O$ was measured by varying the catalytic reaction temperature and the circulating flow rate. $CH_4$ conversion was 99% or more at the catalytic reaction temperature of $650^{\circ}C$ and the circulating flow rate of 2.0 L/min. $H_2O$ conversion was 96% or more at the catalytic reaction temperature of $375^{\circ}C$ and the circulating flow rate of 1.8 L/min. In addition, the amount of $CQ_4$ generated by Korean Demonstration Fusion Power Plant (K-DEMO) in the future was predicted. Then, the treatment process for the $CQ_4$ was proposed and HAZOP (hazard and operability) analysis was conducted to identify the risk factors and operation problems of the process.

Development of a Mobile Tower-yarder with Tractor (I) - Design and Manufacture - (트랙터부착형 타워집재기 개발(I) - 설계 및 제작-)

  • Park, Sang-Jun;Kim, Bo-Kyun
    • Journal of Korean Society of Forest Science
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    • v.97 no.1
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    • pp.61-70
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    • 2008
  • This study was conducted to develop a mobile tower-yarder with tractor for agriculture and forestry that is the efficient yarder in steep terrains, thinning operation and small scale logging operation. It was designed and manufactured that the power source of tower-yarder is equiped three hydraulic pump connected to PTO of tractor, and three hydraulic pump is used to operate the four motor for drum, the cylinder for clutch of interlocker, the cylinder for tower expanding and the out-rigger cylinder. It was to adopt the running skyline system and the inter-lock function, and to equip the double capstan drum, the storage drum and the clutch for interlock in the development of tower-yarder. It was to develop the tower-yarder which the winch torque of double-capstan drum, the traction force of double-capstan drum, the number of rotation of double-capstan drum and the line speed is $191kg{\cdot}m$, 1,910 kgf, 220.5 rpm and 138.5 m/min, respectively. And it was known that the optimum flange diameter of the main and haulback storage drum is about 360 mm and about 460 mm in order to storage the main line length of 250m and the haulback line length of 450 m. The carriage was made to adopt the running skyline system and to equip the lock function in order to the convenience of chocking and the fall down preventing of tree. It was provided to develop the wire remote controller for the inter-lock function, the convenience of control and the efficiency of yarding. In development process, this tower-yarder was attached the 3-point linkage hitch equipment and the tire wheel for the traction and moving of tower-yarder. Also, it was equipped that the out-rigger and the guy line in order to raise the safety and efficiency of yarding of tower-yarder.

A Design of PLL and Spread Spectrum Clock Generator for 2.7Gbps/1.62Gbps DisplayPort Transmitter (2.7Gbps/1.62Gbps DisplayPort 송신기용 PLL 및 확산대역 클록 발생기의 설계)

  • Kim, Young-Shin;Kim, Seong-Geun;Pu, Young-Gun;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.21-31
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    • 2010
  • This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

A Dual Charge Pump PLL-based Clock Generator with Power Down Schemes for Low Power Systems (저 전력 시스템을 위한 파워다운 구조를 가지는 이중 전하 펌프 PLL 기반 클록 발생기)

  • Ha, Jong-Chan;Hwang, Tae-Jin;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.11
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    • pp.9-16
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    • 2005
  • This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

Improved Radiochemical Yields, Reliability and Improvement of Domestic $^{18}F$-FDG Auto Synthesizer (국산 $^{18}F$-FDG Auto Sysnthesizer의 수율 향상과 성능 개선)

  • Park, Jun-Hyung;Im, Ki-Seop;Lee, Hong-Jin;Jeong, Kyung-Il;Lee, Byung-Chul;Lee, In-Won
    • The Korean Journal of Nuclear Medicine Technology
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    • v.13 no.3
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    • pp.147-151
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    • 2009
  • Purpose: 2-[$^{18}F$]Fluoro-2-deoxy-D-glucose ([$^{18}F$]FDG) particularly plays as a important role in Positron Emission Tomography (PET) imaging in nuclear medicine. Domestic [$^{18}F$]FDG auto synthesizers are installed in Seoul National University Bundang Hospital (SNUBH) at June 2008, these modules were known that it's synthetic yields were guaranteed in average $45{\pm}5%$ so far. To improve yields and convenience of domestic [$^{18}F$]FDG auto synthesizer, numerous trials in reaction time, base concentration, pressure and temperature were performed to increase [$^{18}F$]FDG yields. Materials and Methods: Several synthetic factors (temperature, time and pressure) and shortcoming were corrected based on many evaporation test. Syringe dispensing of tetra-butylammonium bicarbonate (TBAB) was replaced with micro pipette to prepare tetrabutyl ammonium fluoride salt ([$^{18}F$]TBAF). Troublesome refill of liquid nitrogen every 2 hours which was used to protect vacuum system was changed to charcoal cartridge, base guard filter. To monitor the volume of delivered $[^{18}O]OH_2$ from cyclotron by surveillance camera, we set up the volumetric vial on the cover of the module. In addition to, the recovery vial was added in [$^{18}F$]FDG production system to recover [$^{18}F$]FDG loss due to the leak of valve ($V_{13,14}$) in [$^{18}F$]FDG purification process. Results: When we used micro pipette for adding TBAB ($30\;{\mu}L$ in 12% $H_2O$ in acetonitrile), this quantitative dispensation has enabled to improve $5.5{\pm}1.7%$ residual fluorine-18 activity in fluorine separation cartridge compared to syringe adding. Besides, the synthetic yields of [$^{18}F$]FDG has increased $58{\pm}2.6%$ (n=19), $58{\pm}2.9%$ (n=14), $60%{\pm}2.5%$ (n=17) for 3 months. The life cycle of charcoal cartridge and base vacuum was 3 months prior to filling liquid nitrogen every 2 hours and additional side separator can prevent pump corrosion by organic solvent. After setting of volumetric indicator vial, the operator can easily monitor the total volume of irradiated $[^{18}O]OH_2$ from cyclotron. The recovery vial can be used for the stabilizer when an irregular [$^{18}F$]FDG loss was generated by the leak of valves ($V_{13,14}$). Conclusions: We has optimized appropriate synthetic conditions (temperature, time, pressure) in domestic [$^{18}F$]FDG auto synthesizer. In addition to, the remodeling with several accessories improve yields of domestic [$^{18}F$]FDG auto synthesizer with reliable reproducibility.

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A Study on Rheology Properties of High Performance Wet-mix Shotcrete (고성능 습식 숏크리트의 레올로지에 관한 기초연구)

  • Choi, Sung-Yong;Yun, Kyong-Ku;Kim, Jin-Woung;Kim, Yong-Bin
    • Journal of the Korean Society of Hazard Mitigation
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    • v.10 no.4
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    • pp.25-32
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    • 2010
  • High performance shotcrete has been recently researched partly as a result of high consensus on high strength and durability. However, they are very initial step compared from the advanced countries. For instance, they has been mainly on high strength or durability without any consideration on pumpability and shootability which are very crucial on workability. The purpose of this dissertation was to make a high performance wet-mix shotcrete (high workability) which would solve the general problems of wet-mix process in Korea. For this, the main experimental variables were selected to be silica fume(0.0, 4.5, 9%), air entrained agent(0.0, 0.005%). Rheology with IBB rheometer was measured for evaluating pumpability and shootability as well as pump pressure, rebound rate and build-up thickness. The conclusions from a series of experiments were as follow: The results of analyzing the effects of AE agent and silica fume on rheology indicated that AE agent reduced both of flow resistance(G) and torque viscosity(H) and silica fume increased flow resistance (G) and reduced torque viscosity(H). An increase in the value of torque viscosity(H) produces an increase in the requried pumping pressure. These result indicated that the reduction of torque would work better at improving pumpability. And an increase flow resistance(G) improved shootability(increase build-up thickness and reduce rebound).

A 5.4Gb/s Clock and Data Recovery Circuit for Graphic DRAM Interface (그래픽 DRAM 인터페이스용 5.4Gb/s 클럭 및 데이터 복원회로)

  • Kim, Young-Ran;Kim, Kyung-Ae;Lee, Seung-Jun;Park, Sung-Min
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.2
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    • pp.19-24
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    • 2007
  • With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

Upconversion luminescence from poly-crystalline Yb3+, Er3+ co-doped NaGd(MoO4)2 by simple solid state method (Er3+, Yb3+ 이온이 동시 도핑된 NaGd(MoO4)2의 업컨버젼 분석)

  • Kang, Suk Hyun;Kang, Hyo Sang;Lee, Hee Ae;Shim, Kwang Bo
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.26 no.4
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    • pp.159-163
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    • 2016
  • Up-conversion (UC) luminescence properties of polycrystalline $Er^{3+}/Yb^{3+}$ doped $NaGd(MoO_4)_2$ phosphors synthesized by a simple solid-state reaction method were investigated in detail. Used to 980 nm excitation (InfraRed area), $Er^{3+}/Yb^{3+}$ co-doped $NaGd(MoO_4)_2$ exhibited very weak red emissions near 650 and 670 nm, and very strong green UC emissions at 540 and 550 nm corresponding to the infra 4f transitions of $Er^{3+}(^4F_{9/2},\;^2H_{11/2},\;^4S_{3/2}){\rightarrow}Er^{3+}(^4I_{15/2})$. The optimum doping concentration of $Er^{3+}$, $Yb^{3+}$ for highest emission intensity was determined by XRD and PL analysis. The $Er^{3+}/Yb^{3+}$ (10.0/10.0 mol%) co-doped $NaGd(MoO_4)_2$ phosphor sample exhibited very strong shiny green emission. A possible UC mechanism for $Er^{3+}/Yb^{3+}$ co-doped $NaGd(MoO_4)_2$ depending on the pump power dependence was discussed.

A 3.2Gb/s Clock and Data Recovery Circuit without Reference Clock for Serial Data Communication (시리얼 데이터 통신을 위한 기준 클록이 없는 3.2Gb/s 클록 데이터 복원회로)

  • Kim, Kang-Jik;Jung, Ki-Sang;Cho, Seong-Ik
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.46 no.2
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    • pp.72-77
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    • 2009
  • In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.