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A 5.4Gb/s Clock and Data Recovery Circuit for Graphic DRAM Interface  

Kim, Young-Ran (Department of Information Electronics Engineering, Ewha Womans University)
Kim, Kyung-Ae (ISD IAE Team, Magnachip Semiconductor Ltd)
Lee, Seung-Jun (Department of Information Electronics Engineering, Ewha Womans University)
Park, Sung-Min (Department of Information Electronics Engineering, Ewha Womans University)
Publication Information
Abstract
With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.
Keywords
CDR; CMOS; GDDR; Half-rate; Serial Links;
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