• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.7
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• pp.9-15
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digital loop filter is combined with an error symbol detecting circuit. Suppressing the tracking process, when hop mute and impulse noises are detected, improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. Simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1532-1539
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digial loop filter is combined with an error symbol detecting circuit using an adaptive window. Suppressing the tracking process when hop mute and impulse noises are detected improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. The simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.11
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• pp.2010-2016
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• 2007

PID control is windely used to control stable processes, However, its application to integrating processes is less common. In this paper, we proposed a stable PID controller tuning method for integrating processes with time delay using model reduction method. For proposed model reduction method, it disconnect an integrating factor from integrating processes and reduces separate process using reduction method. and it connect an integrating factor to reduced model. We can obtain stable integrating processes using P controller in inner feedback loop and PID tuning is then used to cancel the pole of the feedback loop. This guarantees both robustness and performance. Simulation examples are given to show the good performance of the proposed tuning method comparing with other methods.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.119-121
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• 2007

PID control is windely used to control stable processes, however, its application to integrating processes is less common. In this paper, we proposed a simple PID controller tuning method for integrating processes with time delay to meet a sensitive function $M_s$. With the proposed PID tuning method, we can obtain stable integrating processes using PD controller in inner feedback loop and a loop transfer function with desired stable specification. This guarantees both robustness and performance. Simulation examples are given to show the good performance of the proposed tuning method to other methods.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.308-313
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• 1993

In this paper, the navigation computer design of RPV(remotely piloted vehicle) using GPS is investigated, and its hardware and software structures are described. The proposed hardware adopts the common PC configuration by using 5016A micro PC card and software is divided into several modules such as navigation module, guidance module and control module, etc. The performance of the navigation computer is verified through PILS(process in the loop simulation).

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.12
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• pp.1217-1222
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• 2010

This paper describes the Model-Based Development(MBD) process behind the flight control software of a close-range unmanned aerial vehicle(KUS-9). An integrated development environment was created using a commercial tool(MATLAB $Simulink^{(R)}$), which was utilized to design models for linear/nonlinear simulation, flight control law, operational logic and HILS(Hardware In the Loop Simulation) system. Software requirements were validated through flight simulations and peer reviews during the design process, whereas the models were verified through the application of a DO-178B verification tool. The integrity of automatically generated C code was verified by using a separate S/W testing tool. The finished software product was embedded on two different types of hardware and real-time operating system(uC/OS-II, VxWorks) to perform HILS and flight tests. The key findings of this study are that MBD Technology enables the development of a reusable and an extensible software product and auto-code generation technology allows the production of a highly reliable flight control software under a compressed time schedule.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.82-88
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• 2014

An available capacitance increasing phase-locked loop(PLL) with two voltage controlled oscillator gains has been proposed. In this paper, the available capacitance of loop filter is increased by using two positive/negative gains of voltage controlled oscillator (VCO). It results in 1/10 reduction in the size of loop filter capacitor. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and a locking time of conventional PLL.

• Proceedings of the Korean Geotechical Society Conference
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• 2010.09a
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• pp.800-807
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• 2010

In this study, a series of numerical analyses has been performed in order to evaluate the performance of a full-scale closed-loop vertical ground heat exchanger constructed in Wonju. The circulation pipe HDPE, borehole and surrounding ground were modeled using FLUENT, a finite-volume method (FVM) program, for analyzing the heat transfer process of the system. Two user-defined functions (UDFs) accounting for the difference in the temperatures of the circulating inflow and outflow water and the change of the surrounding ground temperature with depth were adopted in the FLUENT model. The thermal properties of materials estimated in laboratory were used in the numerical analyses to compare the thermal efficiency of the cement grout with that of the bentonite grout used in the construction. The results of the simulation provide a verification of the in situ thermal response test data. The numerical model with the ground thermal conductivity of 4W/mK yielded the simulation result closer to the in-situ thermal response test than with the ground thermal conductivity of 3W/mK. From the results of the numerical analyses, the effective thermal conductivities of the cement and bentonite grouts were obtained to be 3.32W/mK and 2.99 W/mK, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.6
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• pp.9-14
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• 2002