• Proceedings of the KSME Conference
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• 2004.04a
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• pp.1261-1266
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• 2004

Dielectric Barrier Discharge (DBD) in air, which has been established for the production of large quantities of ozone, is more recently being applied to a wider range of aftertreatment processes for HAPs (Hazardous Air Pollutants). Although DBD has high electron density and energy, its potential use as precharging nano and submicron particles are not well known. In this work, we measured I-V characteristics of DBD and estimated collection efficiency of the particles by DBD type 2-stage ESP. To examine the particle collection with various applied voltage waveforms of DBD for nano and submicron sized, bimodal particles were generated by a electrical tube furnace and an atomizer.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.312-320
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• 2019

In this paper, we design a 512Kb eFlash IP using 110nm eFlash cells. We proposed eFlash core circuit such as row driver circuit (CG/SL driver circuit), write BL driver circuit (write BL switch circuit and PBL switch select circuit), read BL switch circuit, and read BL S/A circuit which satisfy eFlash cell program, erase and read operation. In addition, instead of using a cross-coupled NMOS transistor as a conventional unit charge pump circuit, we propose a circuit boosting the gate of the 12V NMOS precharging transistor whose body is GND, so that the precharging node of the VPP unit charge pump is normally precharged to the voltage of VIN and thus the pumping current is increased in the VPP (boosted voltage) voltage generator circuit supplying the VPP voltage of 9.5V in the program mode and that of 11.5V in the erase mode. A 12V native NMOS pumping capacitor with a bigger pumping current and a smaller layout area than a PMOS pumping capacitor was used as the pumping capacitor. On the other hand, the layout area of the 512Kb eFlash memory IP designed based on the 110nm eFlash process is $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.144-151
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• 2022

In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.

• The KIPS Transactions:PartA
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• v.16A no.1
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• pp.27-34
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• 2009

Recently, power saving with high performance is one of the hot issues in the mobile systems. Various technologies are introduced to achieve low-power processors, which include sub-micron semiconductor fabrication, voltage scaling, speed scaling and etc. In this paper, we introduce a new method that reduces of energy loss at the data cache. Our methods take the benefits in terms of speed and energy loss using selective way precharging of way prediction with concurrent way selecting. By the simulation results, our method achieves 10.2% energy saving compared to the way prediction method, and 56.4% energy saving compared to the common data cache structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.45-53
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• 2003

This paper describes a Unified Voltage Generator that merges the pumping capacitors of boosted voltage generator (VPP) and substrate voltage generator (VBB) for DRAM. This unified voltage generator simultaneously supplies VPP and VBB voltages by using one pumping capacitor and one oscillator. The proposed generator is realized by 0.14${\mu}{\textrm}{m}$DRAM process. The generator reduces the power consumption to 30%, the area of total generator to 40% and the area of pumping capacitor to 29.6%, and improves the pumping efficiency to 13.2% at 2.0V supply voltage. In addition, the generator adopts the charge recycling technique for precharging the pumping capacitor during the period of precharge, thatcan reduces the precharge current to 75%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.88-94
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• 2011

In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the non-programmed eFuse is reduced from 728 ${\mu}A$ to 61 ${\mu}A$ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 $k{\Omega}$ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.10-16
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• 1999

This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.455-461
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• 2017

In this paper, a local DL (Data Line) sensing method with smaller parasitic capacitance replacing the previous distributed DB sensing method with large parasitic capacitance is proposed to reduce the time to transfer BL (Bit Line) voltage to DL in the read mode. A new BL switching circuit turning on NMOS switches faster is also proposed. Furthermore, the access time is reduced to 35.63ns from 40ns in the read mode and thus meets the requirement since BL node voltage is clamped at 0.6V by a DL clamping circuit instead of precharging the node to VDD-VT and a differential amplifier are used. The layout size of the designed 512Kb EEPROM memory IP based on a $0.13{\mu}m$ BCD is $923.4{\mu}m{\times}1150.96{\mu}m$ ($=1.063mm^2$).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.567-574
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• 2015

In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2209-2216
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• 2011

In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.