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http://dx.doi.org/10.17661/jkiiect.2022.15.2.144

Design of Low-Area DC-DC Converter for 1.5V 256kb eFlash Memory IPs  

Kim, YoungHee (Department of Electronic Engineering, Changwon National University)
Jin, HongZhou (Department of Electronic Engineering, Changwon National University)
Ha, PanBong (Department of Electronic Engineering, Changwon National University)
Publication Information
The Journal of Korea Institute of Information, Electronics, and Communication Technology / v.15, no.2, 2022 , pp. 144-151 More about this Journal
Abstract
In this paper, a 1.5V 256kb eFlash memory IP with low area DC-DC converter is designed for battery application. Therefore, in this paper, 5V NMOS precharging transistor is used instead of cross-coupled 5V NMOS transistor, which is a circuit that precharges the voltage of the pumping node to VIN voltage in the unit charge pump circuit for the design of a low-area DC-DC converter. A 5V cross-coupled PMOS transistor is used as a transistor that transfers the boosted voltage to the VOUT node. In addition, the gate node of the 5V NMOS precharging transistor is made to swing between VIN voltage and VIN+VDD voltage using a boost-clock generator. Furthermore, to swing the clock signal, which is one node of the pumping capacitor, to full VDD during a small ring oscillation period in the multi-stage charge pump circuit, a local inverter is added to each unit charge pump circuit. And when exiting from erase mode and program mode and staying at stand-by state, HV NMOS transistor is used to precharge to VDD voltage instead of using a circuit that precharges the boosted voltage to VDD voltage. Since the proposed circuit is applied to the DC-DC converter circuit, the layout area of the 256kb eFLASH memory IP is reduced by about 6.5% compared to the case of using the conventional DC-DC converter circuit.
Keywords
Battery Application; DC-DC Converter; eFlash; IP; Small Area;
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