The Journal of Korea Institute of Information, Electronics, and Communication Technology (한국정보전자통신기술학회논문지)

Korea Information Electronic Communication Technology (한국정보전자통신기술학회)
권호 표지
DOI QR코드

DOI QR Code

Design of an Embedded Flash IP for USB Type-C Applications

USB Type-C 응용을 위한 Embedded Flash IP 설계

  • Kim, Young-Hee (Department of Electronic Engineering, Changwon National University) ;
  • Lee, Da-Sol (Department of Electronic Engineering, Changwon National University) ;
  • Jin, Hongzhou (Department of Electronic Engineering, Changwon National University) ;
  • Lee, Do-Gyu (Department of Electronic Engineering, Changwon National University) ;
  • Ha, Pan-Bong (Department of Electronic Engineering, Changwon National University)
  • Received : 2019.06.13
  • Accepted : 2019.06.26
  • Published : 2019.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we design a 512Kb eFlash IP using 110nm eFlash cells. We proposed eFlash core circuit such as row driver circuit (CG/SL driver circuit), write BL driver circuit (write BL switch circuit and PBL switch select circuit), read BL switch circuit, and read BL S/A circuit which satisfy eFlash cell program, erase and read operation. In addition, instead of using a cross-coupled NMOS transistor as a conventional unit charge pump circuit, we propose a circuit boosting the gate of the 12V NMOS precharging transistor whose body is GND, so that the precharging node of the VPP unit charge pump is normally precharged to the voltage of VIN and thus the pumping current is increased in the VPP (boosted voltage) voltage generator circuit supplying the VPP voltage of 9.5V in the program mode and that of 11.5V in the erase mode. A 12V native NMOS pumping capacitor with a bigger pumping current and a smaller layout area than a PMOS pumping capacitor was used as the pumping capacitor. On the other hand, the layout area of the 512Kb eFlash memory IP designed based on the 110nm eFlash process is $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$.

본 논문에서는 110nm eFlash 셀을 사용한 512Kb eFlash IP를 설계하였다. eFlash 셀의 프로그램, 지우기와 읽기 동작을 만족시키는 row 구동회로(CG/SL 구동회로), write BL 구동회로( write BL 스위치 회로와 PBL 스위치 선택 회로), read BL 스위치 회로와 read BL S/A 회로와 같은 eFlash 코어회로(Core circuit)를 제안하였다. 그리고 프로그램 모드에서 9.5V와 erase 모드에서 11.5V의 VPP(Boosted Voltage) 전압을 공급하는 VPP 전압 발생기회로는 기존의 단위 전하펌프 회로로 cross-coupled NMOS 트랜지스터를 사용하는 대신 body 전압을 ground에 연결된 12V NMOS 소자인 NMOS 프리차징 트랜지스터의 게이트 노드 전압을 부스팅하는 회로를 새롭게 제안하여 VPP 단위 전하펌프의 프리차징 노드를 정상적으로 VIN(Input Voltage) 전압으로 프리차징 시켜서 VPP 전하펌프 회로의 펌핑 전류를 증가시켰다. 펌핑 커패시터로는 PMOS 펌핑 커패시터에 비해 펌핑전류가 크고 레이아웃 면적이 작은 12V native NMOS 펌핑 커패시터를 사용하였다. 한편 110nm eFlash 공정을 기반으로 설계된 512Kb eFlash 메모리 IP의 레이아웃 면적은 $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$이다.

Keywords

JBJTBH_2019_v12n3_312_f0001.png 이미지

그림 1. 1세대 SuperFlash 셀의 공정단면도. Fig. 1. Process cross-section of a 1st generation SuperFlash cell.

JBJTBH_2019_v12n3_312_f0002.png 이미지

그림 2. Row 구동회로. Fig. 2. Row driver circuit.

JBJTBH_2019_v12n3_312_f0003.png 이미지

그림 3. Write 모드시 BL 구동회로 (a) WBL 스위치 회로 (b) PBL 스위치 선택회로. Fig. 3. BL drive circuit in write mode: (a) WBL switching circuit and (b) PBL switch select circuit.

JBJTBH_2019_v12n3_312_f0004.png 이미지

그림 4. Read BL 스위치 회로. Fig. 4. Read BL switch circuit.

JBJTBH_2019_v12n3_312_f0005.png 이미지

그림 5. 설계된 current S/A 회로[6]. Fig. 5. The designed current S/A circuit[6].

JBJTBH_2019_v12n3_312_f0006.png 이미지

그림 6. 기존의 VPP 단위 전하펌프 회로 (a) cross-coupled NMOS 프리차징 방식[17]. (b) boosted gate 전압을 이용한 NMOS 프리차징 방식[18]. Fig. 6. The conventional VPP unit charge pump circuit: (a) cross-coupled NMOS precharging method[17] and (b) NMOS precharging method using boosted gate voltage[18].

JBJTBH_2019_v12n3_312_f0007.png 이미지

그림 7. 새롭게 제안된 VPP 단위 전하펌프 회로. Fig. 7. Newly proposed VPP unit charge pump circuit.

JBJTBH_2019_v12n3_312_f0008.png 이미지

그림 8. 설계된 512Kb eFlash 메모리 IP의 레이아웃 이미지. Fig. 8. Layout image of the designed 512Kb eFlash memory IP.

JBJTBH_2019_v12n3_312_f0009.png 이미지

그림 9. 셀 어레이 관련 선택된 신호와 선택되지 않은 신호의 출력파형 (a) 프로그램 모드 (b) 지우기 모드. Fig. 9. Output waveforms of selected and unselected signals related to the cell array: (a) program mode and (b) erase mode.

표 1. 설계된 512Kb eFlash IP의 주요 특징. Table 1. Major specifications of the designed 512Kb eFlash IP.

JBJTBH_2019_v12n3_312_t0001.png 이미지

표 2. 동작모드에 따른 HV 스위칭 파워의 출력전압. Table 2. Output Voltage of HV switching powers according to operating modes.

JBJTBH_2019_v12n3_312_t0002.png 이미지

표 3. VPP 단위 전하펌프 회로에 따른 펌핑 전류 모의실험 결과. Table 3. Simulation results of pumping currents according to VPP unit charge pump circuit.

JBJTBH_2019_v12n3_312_t0003.png 이미지

References

  1. H. Hidaka, "Embedded Flash Memory for Embedded Systems: Technology, Deign for Sub-systems, and Innovations," Springer International Publishing, 2017.
  2. M. Hatanaka et al., "Value Creation in SOC/MCU Applications by Embedded Non-Volatile Memory Evolutions," Asian Solid State Circuits Conference, pp. 38-42, Nov. 2007.
  3. Y. H. Kim et al., "Design of 40ns 512kb EEPROM IP," The 4th ICIECT, pp. 245-256, July 2018.
  4. H. Park et al., " Design of a Cell Verification Module for Large-Density Memories," Journal of KIIECT, vol. 10, no. 2, pp. 176-183, April 2017.
  5. G. S. Cho, et al., "Design of a Small-Area Low-Power, and High-Speed 128-KBit EEPROM IP for Touch Screen Controllers," Journal of KIMIC, vol. 13, no. 12, pp. 2633-2640, Dec. 2009.
  6. Y. H. Kim et al., "A Study on Memory Circuit Architecture," ETRI Research Report, Oct. 2017.
  7. F. Masuoka et al., "A New Flash E2PROM Cell Using Triple Poly Silicon Technology," IEEE IEDM Tech. Digest. pp. 464-467, 1984.
  8. G. Verma et al., "Reliability Performance of ETOX Based Flash Memories", Proc. IEEE IRPS , pp. 158-166, 1988.
  9. S. Kianian et al., "A Novel 3 Volts-Only, Small Sector Erase, High Density Flash E2PROM", Digest of Technical Papers, Symposium on VLSI Technology, pp. 71-72, 1994.
  10. H. Hidaka, "Evolution of Embedded Flash Memory Technology for MCU," IEEE International Conference on IC Design & Technology, pp. 1-4, May 2011.
  11. Y. Tkachev et al., "Floating-Gate Corner-Enhanced Poly-to-Poly Tunneling in Split-Gate Flash Memory Cells," IEEE Trans. on Electron Devices, vol. 59, no. 1, pp. 5-11, Jan. 2012. https://doi.org/10.1109/TED.2011.2171346
  12. Shang-De Ted Chang, "PMOS Memory Cell with Hot Electron Injection Programming and Tunnelling Erasing," US Patent 5,687,118, Nov. 11, 1997.
  13. M. V. Duuren et al., " Performance and Reliability of 2-Transistor FN/FN Flash Arrays with Hafnium Based High-K Inter-Poly Dielectrics for Embedded NVM", IEEE NVSMW, pp. 48-49, 2006.
  14. G. Tao et al., "A Quantittive Study of Endurance Characteristics and Its Temperature Dependance of Embedded Flash Memories with 2T-FNFN NOR Device Architecture", IEEE Trans. on Device and Materials Reliability, vol. 7, no. 2, pp. 304-309, June 2007. https://doi.org/10.1109/TDMR.2007.901411
  15. Danny Pak-Chum Shum, "Two Transistor Flash Memory Cell", US Patent 6,307,781, Oct. 23, 2001.
  16. H. Y. Tsao et al., "Two Transistor Flash Memory Cell For Use in EEPROM Arrays with a Programmable Logic Device", US Patent 6,757,196, June 29, 2004.
  17. P. Favrat, "A High-Efficiency CMOS Voltage Doubler", IEEE JSSC, vol. 33, pp. 410-416, Mar. 1998.
  18. T. H. Kim et al., "VPP Generator Design for Low-Voltage DRAM," Proceedings of the Korean Conference on Semiconductors , pp. 547-548, Feb. 2008.