• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.26-33
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• 2002

In this paper, a new four-quadrant MOS analog multiplier Is proposed using the quarter-square technique, which is based on the quadratic characteristics of MOS transistor operating in the saturation region and the difference operation of a source-coupled differential circuits. The proposed circuit has been fabricated in a p-well CMOS process. The multiplier achieves a total harmonic distortion of less than 1 percent for the both input ranges of 50 percent of power supply, a -3㏈ bandwidth of 30㎒ a dynamic range of 81㏈ and a power consumption of 40㎽. The active chip area is 0.54㎟. The supposed multiplier circuit is simple and adjust high frequency application because one input signal transfer output by one transistor.

• Journal of IKEEE
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• v.14 no.1
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• pp.55-64
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• 2010

In this paper, we proposed the novel TIGBT with an additional p-type MOS structure to achieve the improved trade-off between turn-off and on-state voltage drop(Vce(sat)). These low on-resistance and the fast switching characteristics of the proposed TIGBT are caused by an enhanced electron current injection efficiency which is caused by additional p-type MOS structure. In the simulation result, the proposed TIGBT has the lower on state voltage of 1.67V and the shorter turn-off time of 3.1us than those of the conventional TIGBT(2.25V, 3.4us).

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.63-69
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• 2012

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.1 no.2
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• pp.70-73
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• 1987

This paper itltroduces a simple stair-case PWM using the pseudo-sinusoidal method. In a configuration of controller, the value of sine as a fundamental factor divided into stair-case level and the three-phase PWM inverter is composed by digital compound for each value of stair-case level. The three-phase output pulse at a fixed carrier frequency and a variable reference frequency is obtained under the effect of reduced harmonics. In this experiment, using the power FET as the switching device, 0.5 H.P. induction motor operation is performed when the switching frequency is 20KHz.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.513-514
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• 2006

As power supply managements become more important than before, supplying a stable system voltage is becoming more and more critical. In this study we propose to use the advantage of weak inversion region of MOS transistors. Analog system, which uses weak inversion region, could work in low voltage environment and reduce power consumption. The proposed buck-converter in weak inversion region of MOS transistor has been verified by silicon chip.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1200-1203
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• 2002

A temperature compensated Crystal Oscillator is widely used for the stable frequency source of mobile communication equipments. Recently, it has become necessary to reduce power consumption of TCXOs. In this paper, we have proposed a TCXO using weak inversion MOS transistors and have evaluated its fundamental characteristics.

• Journal of The Korean Association of Information Education
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• v.14 no.4
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• pp.651-658
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• 2010

This paper is to study adequacy of developing tutorial series for primary school students regarding MOS certification and to analyze a validity. In order to analyze a level of difficulty, current primary teaching materials being used after class, in comparison with ICT discretionary hour materials being used through primary discretionary class, were evaluated. It was done by primary teachers with in- depth understanding of a level of difficulty and after class instructors using Likert scale through quantitative analysis. As a result, level of PowerPoint has a satisfactory fit (76%), however, the degree of difficulty of Word and Excel is quite high. On its subject matter, there is quite a dispute with present curriculum. Therefore, in order to introduce MS-Word or Excel, it is necessary to adjust a level of difficulty or related subjects according to the level of students.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.125-127
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• 2003

Lateral MCT(MOS-controlled thyristor)소자의 전기 적 특성 Parameters의 변화에 따른 스위칭 특성을 조사하였다. 제안된 Lateral 구조의 MCT는 채널과 drift영역의 제작과정이 간편하여 ON저항이 작으면서, 대전류용인 전력소자의 제작이 가능할 것으로 사료되는데, SPICE와 MEDICI 시뮬레이션을 이용하여 drift 저항, transit time및 불순물 농도 분포에 따른 전기적 특성을 알아보았다. 불순물의 농도와 채널길이의 변수에 의한 소자의 저항을 변화시켜 U 특성과 주파수 특성을 조사하였는데, 저항이 커질수록 turn-off 시간과 ON 저항은 증가함을 나타냈다.

• ETRI Journal
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• v.20 no.1
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• pp.37-45
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• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.