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A Study on the new four-quadrant MOS analog multiplier using quarter-square technique  

Kim, Won-U (Dept.of Electronics Electric Engineering, Chungang University)
Byeon, Gi-Ryang (Dept.of Electronics Electric Engineering, Chungang University)
Hwang, Ho-Jeong (Dept.of Electronics Electric Engineering, Chungang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.6, 2002 , pp. 26-33 More about this Journal
Abstract
In this paper, a new four-quadrant MOS analog multiplier Is proposed using the quarter-square technique, which is based on the quadratic characteristics of MOS transistor operating in the saturation region and the difference operation of a source-coupled differential circuits. The proposed circuit has been fabricated in a p-well CMOS process. The multiplier achieves a total harmonic distortion of less than 1 percent for the both input ranges of 50 percent of power supply, a -3㏈ bandwidth of 30㎒ a dynamic range of 81㏈ and a power consumption of 40㎽. The active chip area is 0.54㎟. The supposed multiplier circuit is simple and adjust high frequency application because one input signal transfer output by one transistor.
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