• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.70-82
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• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.48-51
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• 2004

In this paper the importance of re-nitridation on a plasma-enhanced chemical-vapor deposited(PECVD) $SiO_2$ stacked on a thermally grown thin-nitrided $SiO_2$ on n-type 4H SiC have been investigated. Without the final re-nitridation process, the leakage current of metaloxidesemiconductor(MOS) was extremely large. It is believed that water and carbon, contamination from the low-thermal budget PECVD process, are the main factors that destroyed the high quality thin-buffer nitrided oxide. After re-nitridation annealing, the quality of the stacked gate oxide was improved. The reasons of this improvement are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제45권8호
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).

• Journal of the Institute of Electronics Engineers of Korea SC
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• 제48권2호
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• pp.15-21
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• 2011

In this paper, an energy management circuit for solar energy harvesting system is designed in $0.35{\mu}m$ CMOS technology. The solar energy management system consists of an ISC(Integrated Solar Cell), a voltage booster, and an MPPT(Maximum Power Point Tracker) control unit. The ISC generates an open circuit voltage of 0.5V and a short circuit current of $15{\mu}A$. The voltage booster provides the following circuit with a supply voltage about 1.5V. The MPPT control unit turns on the pMOS switch to provide the load with power while the ISC operates at MPP. The SEMU(Solar Energy Management Unit) area is $360{\mu}m{\times}490{\mu}m$ including pads. The ISC area is $500{\mu}m{\times}2000{\mu}m$. Experimental results show that the designed SEMU performs proper MPPT control for solar energy harvested from the ISC. The measured MPP voltage range is about 370mV∼420mV.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국정보통신학회 2015년도 추계학술대회
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• pp.458-461
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• 2015

In this paper 2 types of voltage references and a current reference suitable for low-voltage, low-power circuits are proposed and designed with $0.35{\mu}m\;CMOS$ process. MOS transistors operating in weak inversion and bulk-driven technique are utilized to achieve low-voltage and low-power features. The first voltage reference consumes 1.43uA from a supply voltage of 1.2V while it has a reference voltage of 585mV and a TC(Temperature Coefficient) of $6ppm/^{\circ}C$. The second voltage reference consumes 48pW from a supply voltage of 0.3V while having a reference voltage of 172mV and a TC of $26ppm/^{\circ}C$. The current reference consumes 246nA from a supply voltage of 0.75V with a reference current of 32.6nA and a TC of $262ppm/^{\circ}C$. The performances of the designed references have been verified through simulations.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제13권9호
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• pp.1837-1844
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• 2009

In this paper, the circuit of 2 variable ternary adder and multiplier circuit using current mode CMOS are implemented. The presented ternary adder circuit and multiplier circuit using current mode CMOS are driven the voltage levels. We show the characteristics of operation for these circuits simulated by HSpice. These circuits are simulated under $0.18{\mu}m$ CMOS standard technology, $5{\mu}A$ unit current in $0.54{\mu}m/0.18{\mu}m$ ratio of NMOS length and width, and $0.54{\mu}m/0.18{\mu}m$ ratio of PMOS length and width, and 2.5V VDD voltage, MOS model Level 47 using HSpice. The simulation results show the satisfying current characteristics. The simulation results of current mode ternary adder circuit and multiplier circuit show the propagation delay time $1.2{\mu}s$, operating speed 300KHz, and consumer power 1.08mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제38C권3호
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• pp.239-246
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• 2013

The IEEE 802.15.4 offers standard about PHY and MAC layer and features low power, low bandwidth, and low speed data communication. Because of this reason, IEEE 802.15.4 is only within a limited range such as sensor detection and home network; nevertheless, the research about transmission multimedia data like voice packet through wireless sensor networks is conducted widely. In this paper, we proposed the group communication system based on the sensor network. TDMA/TDD MAC based on the IEEE 802.15.4 PHY for voice communication on the sensor network is designed by improvement existing peer-to-peer voice communication on the sensor network and hardware is implemented for group communication. To measure the quality of designed system, mean opinion score (MOS) is obtained from the experiment and verified by using sine wave method. As a result of an experiment, we expect that a many cases of application solution can be developed using presented system.

• Journal of the Institute of Electronics Engineers of Korea SC
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• 제40권3호
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• Journal of Korean Physical Therapy Science
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• 제13권1호
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• pp.29-38
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• 2006

The purpose of this study lies in finding out the effect that variation of pain and body deflection posture has an influence on the static spinal stabilization after having performed spinal stabilization exercise making degenerative disc disease patients an object over 8 weeks using $CENTAUR^{(R)}$, 3-D spinal stabilization training implement. Subjects : 61 of DDD patients were made as an object of this study (mean age: 45.46 years, SD: ${\pm}12.78$, range: 16-68), their average height was 161.87cm, average weight 60.70kg, 12 males and 49 females were involved. Methods: 8 various investigations were performed and varied values were compared with reinvestigation done after having exercised 8 weeks using 3-D $CENTAUR^{(R)}$. We used VAS(Visual Analog Scale) in order to see the variation of pain intensity, MOS(Modified Oswestry Scale) in order to see activities of daily life. Results VAS was lessened from 7.50 to 2.71, limitation of routine life(MOS) from 20.26 to 9.32, there were remarkable differences statistically(p<0.05). As a result of muscular investigation for static spinal stabilization by 8 variations of body deflection, muscular strength were all increased and there were remarkable differences statistically(p<0.05). Conclusions : It has been turned out that pain and limitation of daily life was lessened as a result of making 61 of degenerative disc disease patients exercised 8 weeks using $CENTAUR^{(R)}$, 3-D spinal stabilization training implement, deep muscular power was increased. Thus it has been turned out that 3-D lumbar stabilization exercise has an effect on the spinal muscles strengthening and alleviation of their pain for degenerative disc disease.

• Journal of Korea Multimedia Society
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• 제10권1호
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• pp.49-57
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• 2007

Recently, CMOS RF integration has been widely explored in the wireless communication area to save cost, power, and chip area. The direct conversion architecture, rather than a more conventional super-het-erodyne, has been an attractive choice for single-chip integration because of its many advantages. However, the direct conversion architecture has several fundamental problems to solve in achieving performance comparable to a super-heterodyne counterpart. In this paper, we describe a programmable filter for mobile communication terminals using a direct conversion architecture. The proposed filter can be implemented with the active-RC filter and programmed to meet the requirements of different communication standards, including GSM, DECT and WCDMA. The filter can be tuned to select a detail frequency by changing the gate voltage of the MOS resistors. The gain of the proposed architecture can be programmed from 27dB to 72dB using the filter gain and VGA in 3dB steps.