• Journal of Information Display
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• 제11권1호
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• pp.21-23
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• 2010

A new level shifter using low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) for low-power applications is proposed. The proposed level shifter uses a capacitive-coupling effect and can reduce the power consumption owing to its no-short-circuit current. Its power saving over the conventional level shifter is 72% for a 3.3 V input and a 10 V output.

• 한국재료학회지
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• 제17권4호
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• pp.207-214
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• 2007

We fabricated thermally-evaporated 10 -Ni/(poly)Si and 10 -Ni/1 -Ir/(poly)Si structures to investigate the microstructure of nickel monosilicide at the elevated temperatures required for annealing. Silicides underwent rapid at the temperatures of 300-1200 for 40 seconds. Silicides suitable for the salicide process formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope(TEM) and an Auger depth profile scope were employed for the determination of vertical section structure and thickness. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates shoed low resistance up to 1000 and 800, respectively, while the conventional nickle monosilicide showed low resistance below 700. Through TEM analysis, we confirmed that a uniform, 20 -thick silicide layer formed on the single-crystal silicon substrate for the Ir-inserted case while a non-uniform, agglomerated layer was observed for the conventional nickel silicide. On the polycrystalline silicon substrate, we confirmed that the conventional nickel silicide showed a unique silicon-silicide mixing at the high silicidation temperature of 1000. Auger depth profile analysis also supports the presence of thismixed microstructure. Our result implies that our newly proposed iridium-added NiSi process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• 한국전기전자재료학회논문지
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• 제20권4호
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• pp.308-317
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• 2007

We fabricated thermally-evaporated 10 nm-Ni/(poly)Si and 10 nm-$Ni_{0.5}Co_{0.5}$/(Poly)Si structures to investigate the microstructure of nickel silicides at the elevated temperatures required lot annealing. Silicides underwent rapid annealing at the temperatures of $600{\sim}1100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester was used to investigate the sheet resistances. A transmission electron microscope and an Auger depth profilescope were employed for the determination of vortical microstructure and thickness. Nickel silicides with cobalt on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1100^{\circ}C$ and $900^{\circ}C$, respectively, while the conventional nickle monosilicide showed low resistance below $700^{\circ}C$. Through TEM analysis, we confirmed that a uniform, $10{\sim}15 nm$-thick silicide layer formed on the single-crystal silicon substrate for the Co-alloyed case while a non-uniform, agglomerated layer was observed for the conventional nickel silicide. On the polycrystalline silicon substrate, we confirmed that the conventional nickel silicide showed a unique silicon-silicide mixing at the high silicidation temperature of $1000^{\circ}C$. Auger depth profile analysis also supports the presence of this mixed microstructure. Our result implies that our newly proposed NiCo-alloy composite silicide process may widen the thermal process window for the salicide process and be suitable for nano-thick silicides.

• 전기학회논문지
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• 제66권5호
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• pp.851-856
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• 2017

Research on the edge isolation process of typical polycrystalline silicon solar cells was carried out using laser scribing equipment. The voltage-current characteristics of the solar cell before and after laser scribing were analyzed using a solar simulator. Current density and efficiency increased as the fill factor of the solar cell remained constant after the laser scribing process. The efficiency of the solar cell can be increased in a short time by the edge isolation process performed via a laser scribing process. The polycrystalline silicon solar cell was made into a series electrode, and the efficiency of the solar cell increased because the width of the solar cell was narrowed and the active region was widened by the laser scribing process.

• E2M - 전기 전자와 첨단 소재
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• 제10권10호
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• pp.1034-1040
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• 1997

A solar cell conversion effiency was degraded by grain boundary effect in polycrystalline silicon. Grain boundaries acted as potential barriers as well as recombination centers for the photo-generated carriers. To reduce these effects of the grain boundaries we investigated various influencing factors such as emitter thickness thermal treatment preferential chemical etching of grain boundaries grid design contact metal and top metallization along boundaries. Pretreatment in $N_2$atmosphere and gettering by POCl$_3$and Al were performed to obtain multicrystalline silicon of the reduced defect density. Structural electrical and optical properties of slar cells were characterized before and after each fabrication process. Improved conversion efficiencies of solar cell were obtained by a combination of pretreatment above 90$0^{\circ}C$ emitter layer of 0.43${\mu}{\textrm}{m}$ Al diffusion in to grain boundaries on rear side fine grid finger top Yb metal and buried contact metallization along grain boundaries.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1422-1424
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• 1994

This paper deals with piezoresistive humidity sensor using polycrystalline silicon (Poly-Si ) with membrane in sensors of semiconductor. Poly-Si piezoresistors which have no temperature dependancy are deposited on silicon wafer, membrane is formed with micromachining technology, then polyimide is formed as a hygroscopic layer. Whereas the principle of conventional humidify sensors are based on the change in electrical properties of the material, the humidity induced volume change of a polyimide layer leads to a deformation of a silicon membrane in this case. This deformation is transformed into an output voltage by Poly-Si piezoresistive. Wheatstone bridge. Fabricated piezoresistive humidity sensors showed good linearity, response time, and long term stability.

• 한국전기전자재료학회논문지
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• 제13권2호
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• pp.95-100
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• 2000

For the well-controlled growing in-situ heavily phosphorus doped polycrystalline Si films directly on Si wafer by reduced pressure chemical vapor deposition, a study is made of the two step growth. When in-situ heavily phosphorus doped Si films were deposited directly on Si (100) wafer, crystal structure in the film is not unique, that is, the single crystal to polycrystalline phase transition occurs at a certain thickness. However, the well-controlled polycrtstalline Si films deposited by two step growth grew directly on Si wafers. Moreover, the two step growth, which employs crystallization of grew directly on Si wafers. Moreover, the two step growth which employs crystallization of amorphous silicon layer grown at low temperature, reveals crucial advantages in manipulating polycrystal structures of in-situ phosphorous doped silicon.

• 한국결정성장학회지
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• 제10권6호
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• pp.412-417
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• 2000

High electric field stressed trap distributions were investigated in the thin silicon oxide of polycrystalline silicon gate metal oxide semiconductor capacitors. The transient currents associated with the off time of stressed voltage were used to measure the density and distribution of high voltage stress induced traps. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface in polycrystalline silicon gate metal oxide semiconductor devices. The stress generated trap distributions were relatively uniform the order of $10^{11}$~$10^{12}$ [states/eV/$\textrm{cm}^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}$~$10^{13}$ [states/eV/$\textrm{cm}^2$]. It was appeared that the transient current that flowed when the stress voltages were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• 한국결정성장학회지
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• 제18권1호
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• pp.45-49
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• 2008

태양광 산업의 성장에 따른 개선된 실리콘 잉곳 제조 방법의 개발은 중요한 이슈 중 하나이다. 단결정 실리콘 웨이퍼에 비해 가격 변에서의 유리함으로 인해 현재 다결정 실리콘 웨이퍼가 태양광 시장의 60% 이상을 점유하고 있으며 주조법, 열교환법, 전자기 주조법 등을 포함한 몇 가지 응고 공정들이 개발되어 오고 있다. 이 논문에서는 ADS 법을 이용하여 대형 다결정 실리콘을 성장하기 위한 공정모사를 수행하였다. ADS 법은 적은 열 손실, 짧은 공정 시간 및 효율적인 방향성 응고가 가능하다는 장점을 가지고 있다. ADS 공정의 수치해석은 온도 분포를 확인하기 위해 유체역학을 적용하였고, 공정모사 결과 240 kg 이상의 대형 다결정 실리콘 잉곳의 효율적인 방향성 응고가 가능함을 확인하였다.

• 한국결정성장학회지
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• 제29권2호
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• pp.50-53
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• 2019

박막 태양전지에 주로 적용되는 다결정 규소층을 AIC(Aluminum Induced Crystallization) 공정을 이용하여 제조하였다. 결정립의 확대를 위하여 selective diffusion barrier 사용하였다. 이 diffusion barrier는 $Al_2O_3$ 막을 사용하였다. 공정시간의 단축을 위하여 열처리는 RTA(Rapid Thermal Annealing) 공정으로 진행하였다. 비정질 실리콘의 결정화는 XRD 측정을 통해 분석했다. 그 결과 $500^{\circ}C$에서 결정화되었으며, 결정 크기는 $15.9{\mu}m$로 계산되었다.