• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.2
• /
• pp.408-414
• /
• 2014

This paper proposes a charge-pump phase-locked loop (PLL) with 51-phase output clock of a 125 MHz target frequency. The proposed PLL uses three voltage controlled oscillators (VCOs) to generate 51-phase clock and increase of maximum operating frequency. The 17 delay-cells consists of each VCO, and a resistor averaging scheme which reduces the phase mismatch among 51-phase clock combines three VCOs. The proposed PLL uses a 65 nm 1-poly 9-metal CMOS process with 1.0 V supply. The simulated peak-to-peak 지터 of output clock is 0.82 ps at an operating frequency of 125 MHz. The differential non-linearity (DNL) and integral non-linearity (INL) of the 51-phase output clock are -0.013/+0.012 LSB and -0.033/+0.041 LSB, respectively. The operating frequency range is 15 to 210 MHz. The area and power consumption of the implemented PLL are $580{\times}160{\mu}m^2$ and 3.48 mW, respectively.

• Journal of Communications and Networks
• /
• v.7 no.3
• /
• pp.248-257
• /
• 2005

In this paper, we develop design procedures for carrier tracking loop for orthogonal frequency division multiplexing (OFDM) systems or other systems of blocked data. In such communication systems, phase error measurements are made infrequent enough to invalidate the traditional loop design methodology which is based on analog loop design. We analyze the degradation in the OFDM schemes caused by the tracking loop and show how the performance is dependent on the rms phase error, where we distinguished between the effect of the variance in the average phase over the symbol and the effect of the phase change over the symbol. We derive the optimal tracking loop including optional delay in the loop caused by processing time. Our solution is general and includes arbitrary phase noise apd additive noise spectrums. In order to guarantee a well behaved solution, we have to check the design against margin constraints subject to uncertainties. In case the optimal loop does not meet the required margin constraints subjected to uncertainties, it is shown how to apply a method taken from control theory to find a controller. Alternatively, if we restrict the solution to first or second order loops, we give a simple loop design procedure which may be sufficient in many cases. Extensions of the method are shown for using both pilot symbols and data symbols in the OFDM receiver for phase tracking. We compare our results to other methods commonly used in OFDM receivers and we show that a large improvement can be gained.

• Proceedings of the KIEE Conference
• /
• 2005.04a
• /
• pp.143-145
• /
• 2005

A typical method to control the single-phase power converter system is to utilize the zero-crossing PLL. However, this method is vulnerable to the voltage disturbance and affects the performance of controller. This paper proposes a new single-phase PLL system that is composed of the adaptive linear combiner and the PI control. The operational principle was analyzed through theoretical approach and the performance was verified through simulations with MATLAB. The proposed PLL system shows rapidness and robustness in control under the voltage disturbances such as the sag, harmonics, and phase jump.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.48 no.12
• /
• pp.28-34
• /
• 2011

In this paper, a PLL frequency synthesizer for RSSI applications is designed by phase noise analysis. Required synthesizer performance is achieved by optimizing the noise performance of PLL components and a loop transfer function, since its phase noise, lock time, and spur suppression capability are determined by the performance of loop components and loop filter characteristics. As an application example, a PLL frequency synthesizer for RSSI applications, which operates at the frequency of 2.288GHz, is designed using the phase noise analysis. The validity of the design technique is proved by experiments.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.7
• /
• pp.1552-1558
• /
• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Proceedings of the KIPE Conference
• /
• 2014.11a
• /
• pp.87-88
• /
• 2014

The paper presents a novel phase locked loop(PLL) control method for robust three-phase thyristor dual converters under sag, notch, and phase loss conditions. This method is applied to three line to line voltages of grid to derive three phase angle errors from three separated single-phase PLLs. They can substitute for abnormal phase to guarantee the synchronization in the various grid fault conditions. The performance of novel PLL with moving average method is verified through simulations.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.15 no.2
• /
• pp.89-94
• /
• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.13 no.3
• /
• pp.206-212
• /
• 2008

This paper proposes the PLL(Phase-Locked Loop) algorithm by a new FFT(Fast Fourier Transform) in a grid-connected PV PCS(Photovoltaics Power Conditionning System). The grid-connected inverter that is applied in a new renewable energy field needs the grid phase information for synchronism. Unlike the PLL which is normally used by three phase D-Q conversion, the preposed PLL algorithm using FFT has non-gain tuning and the powerful noise elimination by the characteristics of FFT. Both simulation and experimental result show that proposed algorithm has the good capacity.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.11
• /
• pp.2495-2502
• /
• 2012

This paper presents a new structure of phase looked loop (PLL) for replacing a process sensitive resistor in loop filter with an additional charge pump (CP). The additional charge pump works as a resistor in a loop filter. The output of two charge pumps changes same direction according to process variation. The simulation results according to process conditions(SS/TT/FF) demonstrate that the proposed PLL works properly with process variations. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by simulation with HSPICE.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.67 no.11
• /
• pp.1447-1454
• /
• 2018

In this paper, the design of robust DSC-PLL(Delayed Signal Cancellation Phase Locked Loop) is proposed for coping with frequency variation. This method shows significant performance for detection of fundamental positive sequence component voltage when the grid voltage is polluted by grid unbalance and frequency variation. The feedback frequency estimation of DSC-PLL is tracking the drift in the phase by unbalance and frequency variation. The robust DSC PLL is to present the analysis on method and performance under frequency variations. These compensation algorithms can correct for discrepancies of changing the frequency within maximum 193[ms] and improve traditional DSC-PLL. Linear interpolation method is adopted to reduce the discretized errors in the digital implementation of the PLL. For verification of robust characteristic, PLL methods are implemented on FPGA with a discrete fixed point based. The proposed method is validated by both Matlab/Simulink and experimental results based on FPGA(XC7Z030).