• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.43-51
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• 2012

This paper presents the design optimization technique for a phase interpolator(PI) and suggests the inductor-loaded PI structure for low power consumption suitable for high-speed applications. An analytical study leads to the design criterion composed of the process constants for the minimum power consumption and the proposed inductor-loaded PI reduces the power by half with determined bandwidth and gain of PI. Designed 7-bit PI using $0.13{\mu}m$ 1.2V CMOS technology consumes $721.2{\mu}W$ in 12GHz with inductor and the suggested optimization technique.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.594-600
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• 2015

A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from $0^{\circ}$ to $360^{\circ}$ with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies $0.047mm^2$. The $jitter_{rms}$ and $jitter_{pk-pk}$ of the output clock are 1.91 ps and 18 ps, respectively.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.217-218
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• 1998

We propose a new digital beamforming algorithm using an interpolation filter in ultrasonic imaging systems. We compared the performances of the proposed algorithm to those of the conventional digital bemforming algorisms, post-beamformer and phase rotation beamformer, by a computer simulation and experiments. The results show that the proposed algorithm has better performance than the others.

• ETRI Journal
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• v.33 no.3
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.7-13
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• 2010

A compact phase interpolator (PI) based spread spectrum clock generator (SSCG) for electromagnetic interference (EMI) reduction is presented. The proposed SSCG utilizes a digitally controlled phase interpolation technique to achieve triangular frequency modulation with less design complexity and small power and area overhead. The novel SSCG can generate the system clock with a programmable center-spread spectrum range of up to +/- 2 % at 200 MHz, while maintaining the clock duty cycle ratio without distortions. The PI-based SSCG has been designed and evaluated in 0.18-um 1.8-V CMOS technology, which consumes about 5.0 mW at 200MHz and occupies a chip size of $0.092mm^2$ including a DLL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.237-244
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• 2003

This paper presents the design of a QPSK/16-QAM downstreams receiver chip. The proposed chip consists of a blind equalizer, a timing recovery block and a carrier recovery block. The blind equalizer uses a DFE sturucture using CMA(Constant Module Algorithm). The symbol timing recovery uses the modified parabolic interpolator. The decision-directed carrier recovery is used to remove the carrier frequency offset, phase offset and phase jitter. The implemented LMDS receiver can support four data rates, 10, 20, 30 and 40 Mbps and can accommodate the symbol rate up to 10 Mbaud. This symbol rate is faster than existing QAM receivers.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.93-96
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• 2000

In this paper, we present an improved novel interpolator that performs high quality interpolation on both synthetic and real world images. Its structure, which is based on a four directional linear predictor with equiripple windowed samples and phase matching equalizer, provides edge-directional data interpolation so that sharp and artifacts-free images are obtained at a reasonable computational cost.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.68-75
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• 2009

In this paper, an efficient proposed CDR(Clock and Data Recovery Circuits) using 1/4-rate clock based on dual-interpolator is proposed. The CDR is aimed to overcome problems that using multi-phase clock to decrease the clock generator frequency causes side effects such as the increased power dissipation and hardware complexity, especially when the number of channels is high. To solve these problems, each recovery part generates needed additional clocks using only inverters, but not flip-flops while maintaining the number of clocks supplied from a clock generator the same as 1/2-rate clock method. Thus, the reduction of a clock generator frequency using 1/4-rate clocking helps relax the speed limitation and power dissipation when higher data rate transfer is demanded.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.574-577
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• 2002

In this paper, we propose a new symbol time synchronization scheme suitable for the OFDM system with an interpolator. The proposed performs the following three steps. In the first step, the coarse symbol time synchronization is achieved by continuously measuring the average power of the received envelope signal. Based on this average power, the detection possibility for the symbol time synchronization is determined. If the signal is sufficient for synchronization, we next perform a relatively accurate symbol time synchronization by measuring the correlation a short training signal and the received envelope signal. Finally, an additional frequency synchronization is performed with a long training signal to correct symbol synchronization errors caused by the phase rotation. From the simulation results, one can see that the proposed synchronization scheme provides a good synchronization performance over frequency selective channels.