• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.865-870
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• 2001

In this paper, we analyse the effect of phase noise from PLL frequency synthesizer on 64 QAM when detecting corrupted signals. To predict the phase noise of an oscillator very accurately, we assume that the oscillator is linearly time-varying when the input impulsive current to the oscillator is small. The performance of the detector which detects the corrupted signal by oscillator phase noise is compared with that when the detector is only affected by AWGN and then analyse how much the phase noise degrades the system performance for 64 QAM.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.955-958
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• 1999

We designed a phase locked loop (PLL), which is applicable to microprocessor clock generation application. The designed PLL has a new simple phase frequency detector (PFD) which eliminate dead-zone and has a good high frequency characteristic. The lock-in range of the designed PLL is 50 MHz ~ 150 MHz at 3.3v power supply voltage. The design is carried out using a 0.6${\mu}{\textrm}{m}$ triple metal CMOS process. The area of the layout is 0.35mm by 0.42mm with 359 transistors.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1643-1647
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• 2003

This paper, we propose a new high noise immunity phase-locked loop(PLL) which can suppress the high incident noise coupling with large amplitude and long period to the input frequency of PLL and keeps constant frequency and phase of the VCO output for providing the high stability distribution clock pulse.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1147-1158
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• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1129-1132
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• 2003

본 논문에서는 위상/주파수 검출기을 설계시 문제가 되는 Reference Spur을 없게 하여 Low Noise를 구현할 수 있는 No Spike PFD(Phase Frequency Detector)를 제안한다. 위상동기루프의 특별한 형태로 차지 펌프 위상동기루프가 있다. 차지 펌프위상동기 루프는 일반적으로 3-state 위상/주파수 검출기를 이용한다. 이 3-state 위상/주파수 검출기는 기준 신호와 VCO 출력 신호의 위상차에 비례하는 디지털 파형으로 출력을 내보낸다. 차지 펌프 위상동기루프 그림 1 처럼 디지털 위상/주파수 검출기(PFD), 차지 펌프(CP), 루프 필터(LF), VCO로 구성된다. PFD 는 기준 신호와 VCO 에 의해 만들어진 출력 신호를 입력받아 각각의 위상과 주파수를 비교한다. 즉, 출력 신호가 기준 신호보다 느릴 때에는 출력 신호를 앞으로 당기기 위해서 up 신호를 넘겨주고, 출력 신호가 기준 신호보다 빠를 때에는 출력 신호를 뒤로 밀기 위해 down 신호를 넘겨준다. 차지 펌프(CP)의 전류를 Ip 라고 한다면, CP 에서 LF 로 흐르거나, LF에서 CP로 흐르는 전류 Ip의 평균량이 기준 신호와 VCO 출력 신호의 위상차에 비례하는 것이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.194-200
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• 2006

A 26.4 GHz phase locked oscillator(PLO) for communication satellite transponder is developed. The PLO consists of fundamental frequency generation module(FFGM) and frequency multiplication part(FMP). The signal of 26.4 GHz is generated through frequency tripling process of 8.8 GHz fundamental frequency. Phase locking technique using sampling phase detector(SPD) is adopted to design the FFGM. The MMIC tripler and amplifier are also designed for the reduction of the size and mass of FMP. The phase noise characteristics are exhibited as -96 dBc/Hz at 10 tHz offset frequency and -105 dBc/Hz at 100 kHz offset frequency, respectively, with the output power over 11 dBm. All performance parameters are complied with the design requirements.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.52-59
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• 1998

New types of PFD (phase-frequency detector) are proposed with reset time and propagation delay reduced. The perfomrance of our proposed PFDs are confirmed by SPICE simulation with 0.8.mu.m CMOS process parameter. As a result of simulation, the reset time of PFDs are 0.32 nsec and 0.030 nsec in capture-process. The proposed PFDs can be used in hihg-speed phase-licked loop (PLL).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2716-2724
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• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Progress in Medical Physics
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• v.3 no.2
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• pp.43-57
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• 1992

Phase detector techique provides a unique probe to membrane recycling phenomenon by enabling dynamic monitoring of cell membrane capacitance. However, it has inherent errors due to constant changes in measurement environments. The present study analyzed several error sources to develope application criteria of this technique. and the following was found based on a theoretical analysis. The initial phase angle has to be appropriately selected to minimize the error due to perturbation of access and membrane conductances. Excitation frequency is also important to determine the initial phase angle. However. deviation of the phase angle from a predetermined initial value during the measurement period does not affect capacitance estimation to a significant degree. Despite an appropriate initial phase selection an error in scaling factor is expected for a large increase in capacitance during exocytosis. which may be overcome by iteratively correcting the scaling factor over the measurement period. These results will provide a useful guideline in practical application of this technique.