• 한국농공학회지
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• 제36권2호
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• pp.111-122
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• 1994

In this study, an algorithm which can be applied to the optimum design of simple steel plate girders was developed, and efficient optimization strategies for the solution of algorithm were found out. The optimum design algorithm consists of 3-levels of optimization. In the first and second levels of optimization, the absolute maximum bending moment and shearing force are extracted and in the third level of optimization, the optimum cross section of steel plate girder is determined. For the optimum design of cross section, the objective function is formulated as the total area of cross section and constraints are derived in consideration of the various stresses and the minimum dimension of flange and web based on the part of steel bridge in the Korea standard code of road bridge. Sequential unconstrained minimization technique using the exterior penalty function method(SUMT-EP), sequential linear programming(SLP) and sequential quadratic programming (SQP) are proved to be efficient and robust strategies for the optimum design of simple plate girder cross section. From the reliable point of view, SLP is the most efficient and robust strategy and SQP is the most efficient one from the viewpoint of converguency and computing time.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제8권5호
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• pp.1654-1675
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• 2014

In practical wireless systems, the erroneous channel state information (CSI) sometimes deteriorates the performance drastically. This paper focuses on robust design of coordinated set planning of coordinated multi-point (CoMP) transmission, with respect to the feedback delay and link error. The non-ideal channel models involving various uncertainty conditions are given. After defining a penalty factor, the robust net ergodic capacity optimization problem is derived, whose variables to be optimized are the number of coordinated base stations (BSs) and the divided area's radius. By the maximum minimum criterion, upper and lower bounds of the robust capacity are investigated. A practical scheme is proposed to determine the optimal number of cooperative BSs. The simulation results indicate that the robust design based on maxmin principle is better than other precoding schemes. The gap between two bounds gets smaller as transmission power increases. Besides, as the large scale fading is higher or the channel is less reliable, the number of the cooperated BSs shall be greater.

• ETRI Journal
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• 제5권3호
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• pp.3-8
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• 1983

복수 설비입지 문제의 한 유형인 컴퓨터 시스템 설치문제는 설치위치의 결정, 서비스 지역의 할본, 각 시스템의 규모 결정 등 복합적인 의사결정 과제를 안고 있다. 이 세가지 의사결정 문제는 상호 밀접하게 연결되어 있으므로 세 문제를 동시에 고려하여 전체적으로 최적화할 수 있는 해를 구하도록 해야하는 데 이는 매우 어려운 일이다. 그러므로 지금까지는 각각의 최적해를 독립적으로 구한 후 이를 적당히 결합한다거나 또는 아예 최적해를 구하기 보다는 만족할 만한 적정해를 구함으로써 만족할 수 밖에 없었다. 본 연구에서는 이러한 한계를 극복하기 위해 컴퓨터 시스템 설치에 있어서의 location-Size결정모형을 구축함으로써 이러한 의사결정 문제의 수리적 최적해를 구하고자 했다. 이 모형은 선형 및 비선형의 제약조건을 갖는 non-linear programming 문제로 수식화 되었으며, penalty function method, feasible conjugate, direction methods, branch & bound technique등의 algorithm들을 단계적으로 사용함으로써 최적해의 도출이 가능하게 되었다. 실제 문제에 적용한 결과 유용성은 충분한 것으로 보여졌으나 해법상의 개선을 통해 계산노력을 줄이도록 함이 요구 되었다.

• 한국정밀공학회지
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• 제14권12호
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• pp.24-29
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• 1997

Recently, Genetic Algorithm(GA), which is a stochastic direct search strategy that mimics the process of genetic evolution, is widely adapted into a search procedure for structural optimization. Contrast to traditional optimal design techniques which use design sensitivity analysis results, GA is very simple in their algorithms and there is no need of continuity of functions(or functionals) any more in GA. So, they can be easily applicable to wide area of design optimization problems. Also, owing to multi-point search procedure, they have higher porbability of convergence to global optimum compared to traditional techniques which take one-point search method. The methods consist of three genetics opera- tions named selection, crossover and mutation. In this study, a method of finding the omtimum size and topology of drilling machine is proposed by using the GA, For rapid converge to optimum, elitist survival model,roulette wheel selection with limited candidates, and multi-point shuffle cross-over method are adapted. And pseudo object function, which is the combined form of object function and penalty function, is used to include constraints into fitness function. GA shows good results of weight reducing effect and convergency in optimal design of drilling machine.

• 한국컴퓨터산업학회논문지
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• 제6권5호
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 한국산업정보학회논문지
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• 제21권1호
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• pp.17-25
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• 2016

본 논문은 동기회로에서 누설 전류를 줄이기 위해서 사용되는 파워 스위치 구조를 결합한 새로운 구조의 저전력 비동기 회로 설계 방법을 제안하고자 한다. Static 방식, Semi-static 방식과 같은 기존의 지연 무관방식의 비동기 방식과 비교해서 다소 속도의 손해는 있지만, 파워 스위치에 의해서 데이터가 없는 상태에서는 누설 전력을 줄일 수 있고, 전체 사이즈가 작아짐으로써 데이터가 입력되는 순간의 스위칭 전력도 줄일 수 있는 장점이 있다. 따라서, 제안된 방법은 속도보다 저전력을 기본으로 하는 사물인터넷 시스템에서 요구되는 전전력 설계 방법이 될 것이다. 본 논문에서는 새로운 방식의 비동기 회로를 사용하여 $4{\times}4$곱셈기를 0.11um 공정으로 설계하고, 기존의 비동기 방식의 곱셈기와 스피드, 누설 전류, 스위칭 파워, 회로 크기 등을 비교하였다.

• 지구물리와물리탐사
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• 제16권3호
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• pp.119-130
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• 2013

자력탐사자료의 3차원 역산법을 개발하였다. 자력탐사자료의 역산에서 가장 문제가 되는 점은 비유일해 문제와 방대한 계산시간이다. 일반적으로 자력탐사자료의 역산은 모델변수의 수가 자료의 수보다 훨씬 많아 비유일해 문제를 더욱 심화시키게 된다. 또한 자력탐사자료는 심도 분해능이 매우 낮다. 비유일해 문제를 극복하기 위하여 분해능이 높은 모델변수에는 큰 제한을 가하고, 작은 모델변수에는 약한 제한을 가하는 분해능 모델제한자를 제안하고, 이를 적용하여 분해능이 낮은 모델변수도 효과적으로 추정할 수 있었다. 또한 대형 행렬식을 웨이블릿 변환을 통하여 희소행렬로 변환하고, 역행렬의 계산에 병렬계산 방식을 적용하여 계산시간을 획기적으로 절감하였다. 수치실험을 통하여 개발된 3차원 역산알고리듬의 타당성을 검토하였다. 또한 금산 지역에서 얻어진 항공자력탐사자료의 역산에 적용하였다.

• 국제초고층학회논문집
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• 제3권1호
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• pp.65-71
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• 2014

Baku, the capital of Azerbaijan, has seen a boom in construction in recent years. The old Baku city has been rapidly transforming into a new hub of high-rise buildings and lively cultural centers hosting the Euro Vision Song Contest in 2012 and European Games in 2015. A major population shift to Baku from its suburbs and the countryside has resulted in the doubling of Baku's population in the 4 years between 2009 and 2013. As of January 2013, Baku's population reached four million people, 43% of the citizens in Azerbaijan according to The State Statistical Committee of Azerbaijan. With this trend, the city needs more high-rise buildings to accommodate rapidly increasing demands for more housing and business space. Until the Azerbaijan Seismic Building Code was published in 2010 and became effective, many different seismic criteria, in terms of building codes and seismic intensities, were used for all new high-rise projects in Baku. Some designers used the SNIP (Russian) code with seismic level 9 or level 8 with 1 point penalty. Others used the Turkish code with Seismic Zone 1, UBC 97 with Zone 2 through 4, or IBC with Sa = 0.75 g through 1.0 g. The seismic intensity is now clarified with the Azerbaijan Seismic Building Code. However, the Azerbaijan Seismic Building Code is appropriate for low-rise buildings applications but may be inappropriate for high-rise project applications. This is because the code-defined response spectrum yields unrealistically conservative seismic forces for high-rise buildings with long periods, as compared to those determined by other internationally accepted building codes. This paper provides observations and recommendations for code-based seismic load assessment of high-rise buildings in the Baku area.

• 대한전자공학회논문지SD
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• 제46권12호
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• pp.36-42
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• 2009

본 논문은 modified Booth 곱셈기를 위한 고성능 파이프라인 구조를 제안하고 있다. 제안하는 곱셈기 회로는 곱셈 속도를 향상시키기 위해 가장 널리 사용되는 기술인 modified Booth 알고리즘과 파이프라인 구조에 기반을 두고 있다. 최적의 파이프라인 곱셈기를 구현하기 위해 많은 실험이 수행되었다. 파이프라인의 단 수가 증가할수록 회로 속도 향상율이 회로 크기 증가율보다 더 크며, 파이프라인 레지스터를 적절한 위치에 삽입하는 것이 중요하다는 사실이 실험 결과를 통해 확인되었다. 제안하는 modified Booth 곱셈기 회로를 Verilog HDL로 설계하였으며 0.13um 표준 셀 라이브러리를 이용하여 게이트 수준 회로로 합성하였다. 합성된 회로는 다른 곱셈기들에 비해 좋은 성능을 나타내었으며, GHz 범위에서 동작할 수 있으므로 광통신 시스템과 같은 극히 높은 성능을 필요로 하는 응용 시스템에서 사용될 수 있다.