Browse > Article

High-performance Pipeline Architecture for Modified Booth Multipliers  

Kim, Soo-Jin (Hankuk University of Foreign Studies)
Cho, Kyeong-Soon (Hankuk University of Foreign Studies)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.12, 2009 , pp. 36-42 More about this Journal
Abstract
This paper proposes the high-performance pipeline architecture for modified Booth multipliers. The proposed multiplier circuits are based on modified Booth algorithm and pipeline architecture which are the most widely used techniques to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The experimental results show that the speed improvement gain exceeds the area penalty and this trend is manifested as the number of pipeline stages increases. It is also important to insert the pipeline registers at the proper positions. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since they operate at GHz ranges, they can be used in the application systems requiring extremely high performance such as optical communication systems.
Keywords
곱셈기;파이프라인 구조;고성능;modified Booth 알고리즘;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Shiann-Rong Kuang, Jiun-Ping Wang and Cang-Yuan Guo, "Modified Booth Multipliers with A Regular Partial Product Array," IEEE Trans. on Circuit and Systems, vol. 56, Issue 5, pp. 404-408, May 2009   DOI   ScienceOn
2 Li-rong Wang, Shyh-Jye Jou and Chung-Len Lee, "A Well-structured Modified Booth Multiplier Design," IEEE International Symposium on VLSI Design, Automation and Test, pp. 85-88, April 2008
3 A. Asati and Chandrashekhar, "An Improved High Speed Fully Piplined 500MHz 8x8 Baugh Wooley Multiplier Design Using 0.6um CMOS TSPC Logic Design Style," IEEE Third International Conference on Industrial and Information Systems, pp. 1-6, Dec. 2008
4 Yung-chin Liang, Ching-ji Huang and Wei-bin Yang, "A 320-MHz 8bit x 8bit Pipelined Multiplier in Ultra-low Supply Voltage," IEEE Asian Solid-state Circuits, pp. 73-76, Nov. 2008
5 C. S. Wallace, "A Suggestion for a Fast Multiplier," IEEE Trans. on Computers. vol. BC13, pp. 14-17, Feb. 1964
6 S. B. Tatapudi and J. G. Delgado-Frias, "Designing Pipelined Systems with a Clock Period Approaching Pipline Register Delay," 48th Midwest Symposium on Circuits and Systems, vol. 1, pp. 871-874, Aug. 2005
7 M. D. Ercegovac and T. Lang, Digital Arithmetic, Morgan Kaufmann Publishersm Los Altos, CA 94022, USA, 2003
8 Jung-Yup Kang and Jean-Luc Gaudiot, "A Simple High-speed Multiplier Design," IEEE Trans. on Computers, vol. 55, issue 10, pp. 1253-1258, Oct. 2006   DOI   ScienceOn
9 A. D. Booth, "A Signed Binary Multiplication Technique," Quarterly J. Mechanical and Applied Math, vol. 4, pp.236-240, 1951   DOI
10 Wen-Chang Yeh and Chein-Wei Jen, "High-speed Booth Encoded Parallel Multiplier Design," IEEE Trans. on Computers, vol. 49, isseu 7, pp. 692-701, July 2000   DOI   ScienceOn
11 Hwang-Cherng Chow and I-Chyn Wey, "A 3.3V 1GHz High Speed Pipelined Booth Multiplier," IEEE ISCAS Symposium on Circuits and Systems, vol. 1, pp. 457-460, May 2002
12 M. Aguirre-Hernandez and M. Linarse-Aranda, "Energy-efficient High-speed CMOS Pipelined Multiplier," 5th International Conference on Electrical Engineering, Computing Science and Automatic Control, pp. 460-464, Nov. 2008
13 A. A. Khatibzadeh, K. Raahemifar and M. Ahmadi, "A 1.8V 1.1GHz Novel Digital Multiplier," Cadadian Conference on Electrical and Computer Engineering, pp. 686-689, May 2005
14 S. Hus, V. Venkatraman, S. Mathew, H. Kaul, M. Anders, S. Dighe, W. Burleson and R. Krishnamurthy, "A 2GHZ 13.6mW 12x9b Mutiplier for Energy Efficient FFT Accelerators," ESSCIRC Proc. of Solid-state Circuits, pp. 199-202, Sept. 2005