• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.5
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• pp.1654-1675
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• 2014

In practical wireless systems, the erroneous channel state information (CSI) sometimes deteriorates the performance drastically. This paper focuses on robust design of coordinated set planning of coordinated multi-point (CoMP) transmission, with respect to the feedback delay and link error. The non-ideal channel models involving various uncertainty conditions are given. After defining a penalty factor, the robust net ergodic capacity optimization problem is derived, whose variables to be optimized are the number of coordinated base stations (BSs) and the divided area's radius. By the maximum minimum criterion, upper and lower bounds of the robust capacity are investigated. A practical scheme is proposed to determine the optimal number of cooperative BSs. The simulation results indicate that the robust design based on maxmin principle is better than other precoding schemes. The gap between two bounds gets smaller as transmission power increases. Besides, as the large scale fading is higher or the channel is less reliable, the number of the cooperated BSs shall be greater.

• ETRI Journal
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• v.5 no.3
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• pp.3-8
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• 1983

In the area of computer network planning, a location-allocation-size problem is involved. Since multi-facility location-allocation-size problems are very complex in formulating a mathematical model, it is a usual practise to adopt alternative approaches, which give no optimal results, instead of the optimal solution by mathematical approach. In this article, however, an attempt is made to formulate a mathematical model for the decision making problem of computer network design.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.12
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• pp.24-29
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• 1997

Recently, Genetic Algorithm(GA), which is a stochastic direct search strategy that mimics the process of genetic evolution, is widely adapted into a search procedure for structural optimization. Contrast to traditional optimal design techniques which use design sensitivity analysis results, GA is very simple in their algorithms and there is no need of continuity of functions(or functionals) any more in GA. So, they can be easily applicable to wide area of design optimization problems. Also, owing to multi-point search procedure, they have higher porbability of convergence to global optimum compared to traditional techniques which take one-point search method. The methods consist of three genetics opera- tions named selection, crossover and mutation. In this study, a method of finding the omtimum size and topology of drilling machine is proposed by using the GA, For rapid converge to optimum, elitist survival model,roulette wheel selection with limited candidates, and multi-point shuffle cross-over method are adapted. And pseudo object function, which is the combined form of object function and penalty function, is used to include constraints into fitness function. GA shows good results of weight reducing effect and convergency in optimal design of drilling machine.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• Geophysics and Geophysical Exploration
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• v.16 no.3
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• pp.119-130
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• 2013

We developed a method for inverting magnetic data to recover the 3D susceptibility models. The major difficulty in the inversion of the potential data is the non-uniqueness and the vast computing time. The insufficient number of data compared with that of inversion blocks intensifies the non-uniqueness problem. Furthermore, there is poor depth resolution inherent in magnetic data. To overcome this non-uniqueness problem, we propose a resolution model constraint that imposes large penalty on the model parameter with good resolution; on the other hand, small penalty on the model parameter with poor resolution. Using this model constraint, the model parameter with a poor resolution can be effectively resolved. Moreover, the wavelet transform and parallel solving were introduced to save the computing time. Through the wavelet transform, a large system matrix was transformed to a sparse matrix and solved by a parallel linear equation solver. This procedure is able to enormously save the computing time for the 3D inversion of magnetic data. The developed inversion algorithm is applied to the inversion of the synthetic data for typical models of magnetic anomalies and real airborne data obtained at the Geumsan area of Korea.

• International Journal of High-Rise Buildings
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• v.3 no.1
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• pp.65-71
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• 2014

Baku, the capital of Azerbaijan, has seen a boom in construction in recent years. The old Baku city has been rapidly transforming into a new hub of high-rise buildings and lively cultural centers hosting the Euro Vision Song Contest in 2012 and European Games in 2015. A major population shift to Baku from its suburbs and the countryside has resulted in the doubling of Baku's population in the 4 years between 2009 and 2013. As of January 2013, Baku's population reached four million people, 43% of the citizens in Azerbaijan according to The State Statistical Committee of Azerbaijan. With this trend, the city needs more high-rise buildings to accommodate rapidly increasing demands for more housing and business space. Until the Azerbaijan Seismic Building Code was published in 2010 and became effective, many different seismic criteria, in terms of building codes and seismic intensities, were used for all new high-rise projects in Baku. Some designers used the SNIP (Russian) code with seismic level 9 or level 8 with 1 point penalty. Others used the Turkish code with Seismic Zone 1, UBC 97 with Zone 2 through 4, or IBC with Sa = 0.75 g through 1.0 g. The seismic intensity is now clarified with the Azerbaijan Seismic Building Code. However, the Azerbaijan Seismic Building Code is appropriate for low-rise buildings applications but may be inappropriate for high-rise project applications. This is because the code-defined response spectrum yields unrealistically conservative seismic forces for high-rise buildings with long periods, as compared to those determined by other internationally accepted building codes. This paper provides observations and recommendations for code-based seismic load assessment of high-rise buildings in the Baku area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.36-42
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• 2009

This paper proposes the high-performance pipeline architecture for modified Booth multipliers. The proposed multiplier circuits are based on modified Booth algorithm and pipeline architecture which are the most widely used techniques to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The experimental results show that the speed improvement gain exceeds the area penalty and this trend is manifested as the number of pipeline stages increases. It is also important to insert the pipeline registers at the proper positions. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since they operate at GHz ranges, they can be used in the application systems requiring extremely high performance such as optical communication systems.

• Journal of Broadcast Engineering
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• v.15 no.5
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• pp.697-702
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• 2010

Contour artifact is known as the unintentional result of quantizing a flat area that has smooth gradients. In this letter, a decontouring algorithm is proposed to efficiently remove false contours that occur in typical block-based video coding applications. First, the algorithm goes through a refinement stage to determine candidate blocks probably having noticeable false contours with different kinds of features in a block. Then, pseudo-random noise masking is applied to those blocks to mitigate the contour artifacts. This block-based selective decontouring can efficiently remove the unnecessary processing of those blocks that have no false contour, which incidentally ensures a minor penalty in visual quality and computational complexity. The proposed algorithm was demonstrated, integrated into H.264/AVC, that visual quality can be significantly enhanced with an ignorable rate-distortion (RD) loss and an minor increase in computational complexity.