• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• ETRI Journal
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• v.26 no.6
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• pp.669-672
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• 2004

To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single-electron pass-transistor logic circuit employing a multiple-tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single-electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3-MTJ inverter circuit is simulated at 15 K with parameters $C_g=C_T=C_{clk}=1\;aF,\;R_T=5\;M{\Omega},\;V_{clk}=40\;mV$, and $V_{in}=20\;mV$. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ-SETD logic is successfully translated to the voltage state logic.

• Journal of IKEEE
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• v.17 no.2
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• pp.214-220
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• 2013

Small area LDO (Low drop-out) regulator with pass transistor using body-driven technique is presented in this paper. The body-driven technique can decrease threshold voltage (Vth) and increase the current ID flowing from drain to source in current. The technique is applied to the pass transistor to reduce size of area and maintain the same performance as conventional LDO regulator. A pass transistor using the technique can reduce its size by 5.5 %. The proposed LDO regulator works under the input voltage of 2.7 V ~ 4.5 V and provides up to 150mA load current for an output voltage range of 1.2 V ~ 3.3 V.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.91-94
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• 2000

This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2697-2701
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• 2012

The yield of OTP devices using anti-fuse MOS capacitor have been affected by the input resistance, the size of the pass transistor and the read transistor, and the readout voltage of programed cell. To investigate the element which gives an effect to yield, we analyze the full map data of the resistance characterization of OTP device and those data in a various experimental condition. As a result, we got the optimum conditions which is necessary to the yield improvement. The optimum conditions are as follows: Input resistance is 50 ohms, the channel length of pass transistor is 10um, read voltage is 2.8 volt, respectively.

• Journal of IKEEE
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• v.24 no.2
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• pp.598-603
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• 2020

In this paper present a Low Drop-Out(LDO) regulator that improves load transient characteristics due to the push-pull pass transistor structure is proposed. Improved load over the existing LDO regulator by improving the overshoot and undershoot entering the voltage line by adding the proposed push-pull circuit between the output stage of the error amplifier inside the LDO regulator and the gate stage of the pass transistor and the push-pull circuit at the output stage. It has a delta voltage value of transient characteristics. The proposed LDO structure was analyzed in Samsung 0.13um process using Cadence's Virtuoso, Spectre simulator.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.152-157
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• 2015

Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.363-367
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• 1999

In this paper, a novel 108-bit conditional sum adder(CSA) with Energy Economized Pass-transistor Logic(EEPL) is proposed. A new architecture is adopted, in order to obtain a high speed operation, which is composed of seven modularized 16-bit CMS's and two separated carry generation block. Further a design technique based on EEPL is proposed to reduce the power consumption. With 0.65${\mu}{\textrm}{m}$ single poly, triple metal, 3.3V CMOS process, its operating speed is about 4.95㎱ and the power consumption is reduced in comparison with that of the conventional adder.

• Journal of IKEEE
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• v.21 no.3
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• pp.264-267
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• 2017

In this paper, A low dropout (LDO) regulator that improves the power supply rejection ratio by using a noise canceling circuit is proposed. The noise rejection circuit between the error amplifier and the pass transistor is designed to reduce the influence of the pass transistor on the noise coming from the voltage source. The LDO regulator has the same regulation characteristics as the conventional LDO regulator. The proposed circuit uses 0.18um process and Cadence's Virtuoso and Specter simulator.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.312-318
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• 2016

This paper presents a 2-6 GHz GaN HEMT power amplifier monolithic microwave integrated circuit (MMIC) with bridged-T all-pass filters and output-reactance-compensation shorted stubs using the $0.25{\mu}m$ GaN HEMT foundry process that is developed by WIN Semiconductors, Inc. The bridged-T filter is modified to mitigate the bandwidth degradation of impedance matching due to the inherent channel resistance of the transistor, and the shorted stub with a bypass capacitor minimizes the output reactance of the transistor to ease wideband load impedance matching for maximum output power. The fabricated power amplifier MMIC shows a flat linear gain of 20 dB or more, an average output power of 40.1 dBm and a power-added efficiency of 19-26 % in 2 to 6 GHz, which is very useful in applications such as communication jammers and electronic warfare systems.