전기전자학회논문지 (Journal of IKEEE)

  • 제24권2호
  • /
  • Pages.598-603
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  • 2020
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  • 1226-7244(pISSN)
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  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
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Push-Pull 패스 트랜지스터 구조 및 향상된 Load Transient 특성을 갖는 LDO 레귤레이터

A Low Drop Out Regulator with Improved Load Transient Characteristics and Push-Pull Pass Transistor Structure

  • Kwon, Sang-Wook (Department of Electronics and Electrical Engineering, Dankook University) ;
  • Song, Bo Bae (Department of Electronics and Electrical Engineering, Dankook University) ;
  • Koo, Yong-Seo (Department of Electronics and Electrical Engineering, Dankook University)
  • 투고 : 2020.06.07
  • 심사 : 2020.06.26
  • 발행 : 2020.06.30
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초록

본 논문에서는 Push-Pull 패스 트랜지스터 구조로 인하여 향상된 Load Transient 특성을 향상시킨 LDO(Low Drop-Out)를 제안하였다. LDO 레귤레이터 내부의 오차증폭기의 출력단과 패스 트랜지스터의 게이트단 사이에 제안된 Push-Pull 회로와 출력단에 Push-Pull 회로를 추가하여 전압 라인에 들어오는 Overshoot, Undershoot를 개선시켜 기존의 LDO 레귤레이터보다 개선된 Load Transient 특성의 델타 피크 전압 값을 갖는다. 제안하는 회로는 Cadence의 Virtuoso, Spectre 시뮬레이션을 이용하여 삼성 0.13um 공정에서 특성을 분석하였다.

In this paper present a Low Drop-Out(LDO) regulator that improves load transient characteristics due to the push-pull pass transistor structure is proposed. Improved load over the existing LDO regulator by improving the overshoot and undershoot entering the voltage line by adding the proposed push-pull circuit between the output stage of the error amplifier inside the LDO regulator and the gate stage of the pass transistor and the push-pull circuit at the output stage. It has a delta voltage value of transient characteristics. The proposed LDO structure was analyzed in Samsung 0.13um process using Cadence's Virtuoso, Spectre simulator.

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참고문헌

  1. Behzad Razavi, "Design of Analog CMOS Integrated Circuits," Hanbit media, pp.353-406, 2011.
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