• 대한전자공학회논문지SD
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• 제46권4호
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• pp.21-27
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• 2009

본 연구에서는 고온에서 Schottky barrier SOI nMOS 및 pMOS의 전류-전압 특성을 분석하기 위해서 Er 실리사이드를 갖는 SB-SOI nMOSFET와 Pt 실리사이드를 갖는 SB-SOI pMOSFET를 제작하였다. 게이트 전압에 따른 SB-SOI nMOS 및 pMOS의 주된 전류 전도 메카니즘을 온도에 따른 드레인 전류 측정 결과를 이용하여 설명하였다. 낮은 게이트 전압에서는 온도에 따라 열전자 방출 및 터널링 전류가 증가하므로 드레인 전류가 증가하고 높은 게이트 전압에서는 드리프트 전류가 감소하여 드레인 전류가 감소하였다. 고온에서 ON 전류가 증가하지만 드레인으로부터 채널영역으로의 터널링 전류 증가로 OFF 전류가 더 많이 증가하게 되므로 ON/OFF 전류비는 감소함을 알 수 있었다. 그리고 SOI 소자나 bulk MOSFET 소자에 비해 SB-SOI nMOS 및 pMOS의 온도에 따른 문턱전압 변화는 작았고 subthreshold swing은 증가하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 추계학술대회 논문집
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• pp.123-127
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• 1992

MOS 커패시터가 이온화 방사선에 노출되었을 경우, MOS 커패시터의 방사선 조사 효과는 소자의 전기적 특성 및 동작 수명에 심각한 영향을 일으킬 수 있다. MOS 커패시터는 (100) 방향의 P-type Si wafer 위에 산화막층을 $O^2$+T.C.E. 분위기에서 성장하였으며, 그 두께는 40~80 nm로 만들었다. MOS 커패시터에 대한 방사선 조사는 $Co^{60}-{\gamma}$선을 사용하였고, 조사선량은 $10^4{\sim}10^8$으로 조사하였다. MOS 커패시터에서 전기적 전도 특성의 방사선 조사효과는 산화막 두께와 조사선량을 변화하면서 측정된 P-type MOS 커패시터는 조사선량에 의해서 강하게 영향을 받는다는 것과 저전계 영역에서의 Ohmic 전류가 전체 선량에 의존한다는 것을 알았다. 이 결과는 방사선 조사에 의해 산화막 트랩전하와 산화막-반도체($SiO_2$-Si)계면 트랩전하에 의해서 설명 할 수 있다.

• 한국전기전자재료학회논문지
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• 제15권3호
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• pp.233-237
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• 2002

A giga-bit DRAM(dynamic random access memory) technology with W/WNx/poly-Si dual gate electrode is presented in 7his papers. We fabricated $0.16\mu\textrm{m}$ CMOS using this technology and succeeded in suppressing short-channel effects. The saturation current of nMOS and surface-channel pMOS(SC-pMOS) with a $0.16\mu\textrm{m}$ gate was observed 330 $\mu\A/\mu\textrm{m}$ and 100 $\mu\A/\mu\textrm{m}$ respectively. The lower salutation current of SC-pMOS is due to the p-doped poly gate depletion. SC-pMOS shows good DIBL(dram-induced harrier lowering) and sub-threshold characteristics, and there was no boron penetration.

• 한국전기전자재료학회논문지
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• 제19권2호
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• pp.126-129
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• 2006

We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

• Asian-Australasian Journal of Animal Sciences
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• 제24권6호
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• pp.844-850
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• 2011

This study was conducted to compare the effects of dietary supplementation of Sodium Gluconate (SG), Mannan Oligosaccharide (MOS) and Potassium Diformate (PDF) on growth performance and small intestinal morphology in nursery piglets. One hundred forty four female piglets ($11.69{\pm}0.71\;kg$) were divided into 4 treatments with six replicates of six pigs each. The pigs received a control diet or diets supplemented with SG, MOS and PDF at 2,500, 3,000 and 8,000 ppm; respectively, for 6 weeks. Supplementation of SG, MOS or PDF increased final body weight, average daily gain and tended to improve feed to gain ratio (p = 0.02, 0.04 and 0.16; respectively), other than average daily feed intake, intestinal pH and the bacterial populations were not influenced by the dietary treatments. SG significantly decreased the ammonia concentration in the caecum (p<0.05) and supplementation of SG, MOS or PDF tended to increase lactic acid and total short chain fatty acid concentration in the caecum (p = 0.08, 0.09; respectively), in addition SG, MOS or PDF slightly increased butyric acid concentration in the caecum (p = 0.14). SG highly significant increased the villous height in jejunum (p<0.01) and supplementing SG, MOS or PDF significantly increased crypt depth in jejunum (p<0.05), moreover, PDF significantly increased villous height and crypt depth ratio in jejunum (p<0.05) compared with control. The dietary treatments did not influence villous height and crypt depth in duodenum and villous height in jejunum (p>0.05). It can be concluded that supplementing SG, MOS or PDF as a feed additive has the potential to improve the growth performance, the intestinal lactic acid bacteria population, intestinal short-chain fatty acid concentration and the intestinal morphology of pigs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.105-106
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• 2005

The impact ionization MOS (I-MOS) transistor with 50nm channel length is presented by using 2-D device simulator ISE-TCAD. The subthreshold slope cannot be steeper than kT/q since the subthreshold conduction is due to diffusion current. As MOSFETs are scaled down, this problem becomes significant and the subthreshold slope degrades which leads an increase in the off-current and off-state power dissipation. The I-MOS is based on a gated p-i-n structure and the subthreshold conduction is induced by impact ionization. The simulation results show that the subthreshold slope is 11.7 mV/dec and this indicates the I-MOS improves the switching speed and off-state characteristics.

• Asian-Australasian Journal of Animal Sciences
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• 제26권1호
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• pp.116-121
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• 2013

The effects of oligosaccharide supplementation on the growth performance, flock uniformity and GIT development of broiler chickens were investigated. Four diets, one negative control, one positive control supplemented with zinc-bacitracin, and two test diets supplemented with mannoligosaccharide (MOS) and fructooligosaccharide (FOS), were used for the experiment. Birds given MOS or FOS had improved body weight (BW) and feed efficiency (FCR), compared to those fed the negative control diet during the 35-d trial period. The effect on FCR became less apparent when the birds got older. FOS and MOS supplementation reduced the pancreas weight as a percentage of BW, with an effect similar to that of the antibiotic, at 35 d of age. Birds given MOS tended to have a heavier bursa (p = 0.164) and lower spleen/bursa weight ratio (p = 0.102) at 35 d of age. MOS and Zn-bacitracin showed a clear improvement on flock uniformity, compared to FOS. The mortality rate was not affected by FOS or MOS.

• Transactions on Electrical and Electronic Materials
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• 제6권1호
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• pp.1-5
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• 2005

Continued scaling of MOS devices requires the formation of the ultra shallow and very heavily doped junction. The simulation and experiment results show that the degradation of pMOS performance in logic and SRAM pMOS devices due to the excessive diffusion of the tail and a large amount of dose loss in the extension region. This problem comes from the high-temperature long-time deposition process for forming the spacer and the presence of fluorine which diffuses quickly to the $Si/SiO_{2}$ interface with boron pairing. We have studied the method to improve the pMOS performance that includes the low-energy boron implantation, spike annealing and device structure design using TCAD simulation.

• 한국정보통신학회논문지
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• 제4권2호
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• pp.297-305
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• 2000

본 논문에서는 다양한 안테나 면적을 가지는 다결정실리콘(poly-Si) 및 폴리사이드(polycide) 게이트 물질을 게이트로 갖는 커패시터 및 n/p-MOS 트랜지스터를 사용하여 AAR(Antenna Area Ratio)의 크기에 따른 플라즈마 피해를 측정 및 분석하였다. 플라즈마 공정에 대한 신뢰도 특성을 조사하기 위해, MOS 소자의 게이트 물질을 달리하여 플라즈마 공정에 대한 초기 특성 및 F-N 스트레스와 hot carrier 스트레스 인가시의 n/p-MOSFET의 열화 특성을 측정한 결과 금속 AR에 의하여 플라즈마 공정의 영향을 받는 것으로 관찰되었다. 폴리사이드 게이트 구조가 다결정실리콘 게이트 구조보다 AAR에 따른 정전류 스트레스 인가시의 TDDB(Time Dependent Dielectric Breakdown)및 게이트 전압의 변화 등과 같은 신뢰성 특성에서 상당히 개선됨을 알 수 있었다. 이는 텅스텐 폴리사이드 형성 공정 중에 불소가 게이트 산화막에 함유되었기 때문인 것으로 설명할 수 있으며, 게이트 물질로 폴리사이드를 사용한 소자에서 플라즈마 영향을 줄일 수 있다는 사실이 차세대 MOS 소자의 게이트 박막으로 폴리사이드 게이트 박막을 활용할 수 있는 가능성을 확인하였다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.234-238
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a $0.25-{\mu}m$ standard CMOS Process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier, Total power dissipation is 7.5 mW.